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TLV320DAC32: Problem with power down

Tomasz Watorowski
Prodigy 40 points
Part Number: TLV320DAC32

Hello everyone,

I am having a great deal of trouble when trying to put the TLV320DAC32 into power down mode in order to achieve lowest possible current consumption. In my system I've configured the TLV320DAC32 to use it's internal LDO since I don't have a 1.8V rail. The LDO_SELECT is driven from a microcontroller pin so that I can disable the LDO when the DAC is not used any longer (I don't know if that's a correct thing to do, but the LDO on it's own adds 2mA to overall current consumption). The 3.0V rail that I power the IOVDD DRVDD and AVDD_DAC is always at 3.0V as it is being used all over the system to power other things.

I've prepared the simplest possible firmware in order to observe the chip's behavior that basically does one job: toggles the reset pin at the start of the execution, while keeping the internal LDO off. This results in 6.5mA being consumed - far from calling it a low power state. Then what I did was to do the RESET toggling while keeping the LDO on and after a short period of time (10ms) bring the LDO to the off state. This in turn resulted in a negligible current consumption (few uA for the entire system) BUT after like a minute or so (of complete inactivity from the side of the MCU as it was put into deep sleep mode) the current rocketed back to 6.5mA!

All of the audio serial interface pins are driven low during the experiment, I2C pins (which were not used in this setup) were kept high by the external pull-ups.

Obviously I am not using the correct sequence to keep the DAC in the power down state, but then again I cannot find any sort of programming manual on the TI website that would describe the correct register programming sequence for bringing the DAC's power up and down. Would you be kind enough to explain to me what excactly should I do in order to achieve the power-down consumption as specified in the DAC's datasheet?

Kind Regards,

Tomek

  • 0
    TI__Guru* 84915 points

    Hi, Tomek,

    Welcome to E2E and thank you for your interest in our products!

    Having the TLV320DAC32 in reset mode should be enough to get the lowest power consumption. Could you provide your TLV320DAC32 schematic portion to have more details about this? Do you have any load connected during this measurement?

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 40 points

    Hello Luis,

    Thanks for your reply, here's the schematic. Please note that here I have a fixed connection for the LDO_SELECT, because I thought that I'll be able to power down the LDO using only RESET and Configuration Registers. Since I've noticed that this is not the case I've resorted to cutting the connection on the PCB between LDO_SELECT and 3.0V and connecting it to GPIO pin of my MCU, which drives it either low or high (pin doesn't float, I've double checked).

    As for your question: No, nothing is connected to the output during the experiment.

    Besides that *little* issue with the power down the chip works flawlessly, audio quality is very good. I was able to get it running in cap-less pseudo-stereo mode in a decent amount of time - so that's a thumbs-up!

    Kind regards,

    Tomek

  • 0 in reply to Tomasz Watorowski
    TI__Guru* 84915 points

    Hi, Tomek,

    Thank you for providing the information above.

    Unfortunately, this issue could be related to a leakage current at the DVDD due to a misuse of the LDO feature.

    As mentioned in the datasheet, the device LDO_SELECT pin must be connected to either IOVDD or ground (IOVSS). Also, when the LDO is bypassed, the DVDD pin must be connected to a 1.8V power supply.

    http://www.ti.com/lit/ds/symlink/tlv320dac32.pdf#page=19

    In this case, you are connecting the DVDD power pin to C33 and no power supply. All power pins must be connected at least to the minimum recommended value. Otherwise, it may affect the device behavior and performance:

    http://www.ti.com/lit/ds/symlink/tlv320dac32.pdf#page=5

    Is it possible to adjust the DVDD and LDO_SELECT pins connections according to these details that I just mentioned?

    Please let me know if you have additional questions or comments.

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 40 points

    Hello Luis,

    I did the experiment with the LDO_SELECT hard-wired to the IOVDD and the chip works as expected, obviously, but the question now is:

    Does this imply that I cannot expect the whole IC current consumption to go below what's specified for the LDO (2mA) when the LDO_SELECT is high, EVEN if chip is in Power Down? That would suggest that the LDO_SELECT is in fact more of a "LDO_ENABLE" and no internal block of the IC controls it's operation, so it stays enabled all the time, no matter what. That, in turn, says that If you want to have power dissipation similar to what's given in the Table 1/Page 20 you need to resort to using an external power source for the DVDD.

    Am I right?

    Kind regards,

    Tomek

  • 0 in reply to Tomasz Watorowski
    TI__Guru* 84915 points

    Hi, Tomek,

    I agree with you. The usage of the LDO_SELECT pin that you were intending to use makes a lot of sense. I would have expected to work with the lowest power consumption under this configuration. Unfortunately, due to the internal design of the LDO, you would need to use an external power source for the DVDD in this case to reach the best saving current mode.

    Please let me know if you have additional questions or comments on this.

    Best regards,
    Luis Fernando Rodríguez S. 

  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 40 points

    Hi Luis,

    Thank you for your time and explanation. For the next hardware revision I'll use the chip's internal LDO, an prepare the whole DAC powering scheme so that it can be gated with the use of external 3.0V LDO with ENABLE functionality. This is probably my safest bet. Thing to keep in mind (for anyone who might be reading) is to gate the power to the I2C pull-ups as well so that no current leaks through them during shutdown.

    Once again, thanks for your help!

    Tomek