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TLV320AIC3106: TLV320AIC3106

Amy Luo
Expert 6895 points
Part Number: TLV320AIC3106


Hi team,

Customer is using TLV320AIC3106 as slave. When I2S is the master, it encounters a phenomenon: TLV320AIC3106 headphone jack does not plug in headphones, I2s will receive codec sent 0x3fff3fff, or 0x3fff0000, 0x00003fff. What might be the problem?

Best Regards,
Amy Luo

  • 0
    TI__Mastermind 22950 points

    Hello Amy,

    I am not quite understanding the issue. 

    Correct me if I am wrong but are you saying that when no headphone jack is plugged in, the codec will send codes  0x3fff3fff, 0x3fff0000,or 0x00003fff? What is the intended operation of the codec? Can you share some scope shots of this issue a long with the CLK signals?

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 30 points

    Hello Aaron,

    Thank you for your reply。you are right !  When not plugged into the headphone jack, the codec will send the code 0x3fff3fff, 0x3fff0000 or 0x00003fff.

    This is the waveform when no headphones are plugged in.  channel 1  is dout, channel 2 is serial clock-sclk, and  channel  3  is frame clock-wclk.

    Regards,

    Qin Yang

  • 0 in reply to yangqin
    TI__Mastermind 22950 points

    Hello Qin,

    Thanks for the clarification and images. Can you provide a little more info?

    • What is the customer trying to achieve?
    • Can you provide register settings and schematic?

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 30 points

    Hello Aaron,

    I want to achieve a loopback effect, that is, codec receives data through mic, and sends it to our FPGA board from dout.

    The FPGA board then sends the data to codec, from din to codec, and through the headphones.

    I will hear what I said in the headphones; but now the data I hear in the headphones has a very loud noise, covering up my own voice,

    when I don't plug in the headphones, I will receive 0x3fff, 0x3fff3fff, 0x3fff0000 These data, so I want to know is not because these data lead to noise.

    The attachments are schematic and register settings.

    Regards,

    Qin Yang

    Fullscreen register_setting.c Download 
    int32_t i2c_write_codec(uint8_t addr, uint8_t data, uint32_t len)
{
  return PLAT_OK;
}

int32_t i2c_read_codec(uint8_t addr, uint8_t *data, uint32_t len)
{

  return PLAT_OK;
}

static void i2c_update_codec_bits(uint16_t start_addr, uint8_t mask, uint8_t value)
{
	uint8_t old=0, new=0;
	i2c_read_codec(start_addr, &old,1);
	new = (old & ~mask) | (value & mask);
	if (old != new)
	{
		i2c_write_codec(start_addr, new , 1);

	}


}

static void aic3106_set_adc_channel(void)
{
	/*0: LINE1L is configured in single-ended mode,0000: Input level control gain = 0 dB
	 *1: Left ADC channel is powered up, 00: Left ADC PGA soft-stepping at once per fs*/
	i2c_write_codec(AIC3106_P0R19, 0x4, 1);


	/*0: LINE1R is configured in single-ended mode,1111: LINE1R is not connected to the right ADC PGA
	 *1: Right ADC channel is powered up,00: Right ADC PGA soft-stepping at once per fS*/
	i2c_write_codec(AIC3106_P0R22, 0x7c, 1);

	/*0: The left ADC PGA is not muted,0x00 Gain=26 dB*/
	i2c_write_codec(AIC3106_P0R15, 0x0, 1);


	/*0: The right ADC PGA is not muted,0x00 Gain=0 dB*/
	i2c_write_codec(AIC3106_P0R16, 0x0, 1);

	/* MICL connect to Left ADC, input level gain = 0dB*/
	i2c_write_codec(AIC3106_P0R17, 0xf, 1);

	/* MICR connect to Right ADC, input level gain = 0dB*/
	i2c_write_codec(AIC3106_P0R18, 0xf0, 1);


	/*10: MICBIAS output is powered to 2.5V,00: If Digital MIC is enabled,
	 * both Left and Right Digital MICs are available*/
	i2c_write_codec(AIC3106_P0R25, 0x80, 1);

}

static void aic3106_set_agc_Cfg(void)
{
	/* AGC configuration */
	/* enable/disable -- bit7;
	 * target level -- bit6-4;
	 * attack time -- bit3-2;
	 * decay time -- bit1-0 */
	uint8_t data;
	/*Left AGC enable, Target gain = -5.5db, Attack time = 20ms, decay time = 500ms*/
	i2c_write_codec(AIC3106_P0R26, 0x8f, 1);

	/*Right AGC enable, Target gain = -5.5db, Attack time = 20ms, decay time = 500ms*/
	i2c_write_codec(AIC3106_P0R29, 0x8f, 1);

	/*AGC Maximum gain applicable 30dB*/

	i2c_write_codec(AIC3106_P0R27, 0x96, 1);
	i2c_write_codec(AIC3106_P0R30, 0x96, 1);

	/* AGC Hysteresis noise threshold*/

	/*Left AGC Hysteresis =3db, noise threshold = -80db */
	i2c_write_codec(AIC3106_P0R28, 0xb6, 1);
	/*Right AGC Hysteresis =3db, noise threshold = -80db */
	i2c_write_codec(AIC3106_P0R31, 0xb6, 1);

	/* Noise detect debounce , signal debounce*/
	/*  Left AGC Noise detect debounce = 512ms, signal debounce = 32ms*/
	i2c_write_codec(AIC3106_P0R34, 0x7f, 1);
	/*  Right AGC Noise detect debounce = 512ms, signal debounce = 32ms*/
	i2c_write_codec(AIC3106_P0R35, 0x7f, 1);
}

static void aic3106_set_dac_channel(void)
{
	uint8_t data;
	/* output for AC-coupled driver configuration */
	i2c_write_codec(AIC3106_P0R14, 0x80, 1);

	/* Left DAC Digital Volume Control = 0dB*/
	i2c_write_codec(AIC3106_P0R43, 0x0, 1);

	/* Right DAC Digital Volume Control = 0dB*/
	i2c_write_codec(AIC3106_P0R44, 0x0, 1);

	/*left and right DAC power up*/
	i2c_write_codec(AIC3106_P0R37, 0xc0, 1);


	/*HPLOUT route to left DAC,Analog Volume =0dB*/
	i2c_write_codec(AIC3106_P0R47, 0x80, 1);

	/*Output level control = 0dB, HPLOUT is not muted,HPLOUT is fully powered up*/
	i2c_write_codec(AIC3106_P0R51, 0xf, 1);


	/* HOROUT route to right DAC,Analog Volume =0d*/
	i2c_write_codec(AIC3106_P0R64, 0x80, 1);

	/*Output level control = 0dB, HPROUT is not muted,HPROUT is fully powered up*/
	i2c_write_codec(AIC3106_P0R65, 0xf, 1);
}

static void aic3106_set_output(void)
{
	uint8_t data;
	/*Output common-mode voltage = 1.5 V,Output soft-stepping = one step per fS*/
	i2c_write_codec(AIC3106_P0R40, 0x40, 1);
	/* Driver power-on time = 400 ms,Driver ramp-up step time = 4 ms*/
	i2c_write_codec(AIC3106_P0R42, 0x8e, 1);


}

static void aic3106_set_volume(int32_t Gain)
{
	/*Reg43 --> Left DAC Digital Volume Control Register*/
	/*Reg44 --> Right DAC Digital Volume Control Register*/
	/*The gain range 0 --> -63.5 dB*/

	//The input argument is 0 --> -63.5, The value is smaller, the volume is louder
	uint8_t data;
	if(Gain != 0)
		data = (-Gain)*2;
	else
		data = 0;

	i2c_update_codec_bits(AIC3106_P0R43,0x7f,data);
	i2c_update_codec_bits(AIC3106_P0R44,0x7f,data);

	i2c_update_codec_bits(AIC3106_P0R47,0x7f,data);
	i2c_update_codec_bits(AIC3106_P0R64,0x7f,data);
	
}

static void aic3106_set_input_filter(void)
{
	/*input signal ButterWorth Filter*/
	uint8_t data;

	/* filter enable*/
	i2c_write_codec(12, 0x5F, 1);

	/*filter coefficient programmable*/
	i2c_write_codec(107, 0xC0, 1);

	/*REG0 :select Page 1*/
	i2c_write_codec(0, 0x01, 1);

	/* N0 -- 527D*/
	/* Left -- Reg65/66*/
	i2c_write_codec(65, 0x50, 1);
	i2c_write_codec(66, 0x12, 1);
	/* Right -- Reg71/72*/
	i2c_write_codec(71, 0x50, 1);
	i2c_write_codec(72, 0x12, 1);

	/* N1 -- AD83*/
	/* Left -- Reg67/68*/
	i2c_write_codec(67, 0xAF, 1);
	i2c_write_codec(68, 0xEE, 1);
	/* Left -- Reg73/74*/
	i2c_write_codec(73, 0xAF, 1);
	i2c_write_codec(74, 0xEE, 1);

	/* D1 --690B */
	/* Left -- Reg69/70*/
	i2c_write_codec(69, 0x62, 1);
	i2c_write_codec(70, 0x37, 1);
	/* Left -- Reg75/76*/
	i2c_write_codec(75, 0x62, 1);
	i2c_write_codec(76, 0x37, 1);
	/*REG0 :select Page 0*/
	i2c_write_codec(0, 0x00, 1);
}



static void aic3106_init()
{

	int32_t i = 0;

	i2c_write_codec(AIC3106_P0R0, 0x0, 1);//page select

	i2c_write_codec(AIC3106_P0R1, 0x80, 1);
	i2c_write_codec(AIC3106_P0R2, 0xaa, 1);
	i2c_write_codec(AIC3106_P0R3, 0x91, 1);
	i2c_write_codec(AIC3106_P0R4, 0x04, 1);
	i2c_write_codec(AIC3106_P0R5, 0x0, 1);
	i2c_write_codec(AIC3106_P0R6, 0x0, 1);
	i2c_write_codec(AIC3106_P0R7, 0x0a, 1);
	i2c_write_codec(AIC3106_P0R8, 0x0, 1);
	i2c_write_codec(AIC3106_P0R9, 0x0, 1);
	i2c_write_codec(AIC3106_P0R10, 0x01, 1);
	i2c_write_codec(AIC3106_P0R11, 0x01, 1);
	
	i2c_write_codec(AIC3106_P0R14, 0x80, 1);
	i2c_write_codec(AIC3106_P0R15, 0x7f, 1);
	i2c_write_codec(AIC3106_P0R16, 0x7f, 1);
	i2c_write_codec(AIC3106_P0R17, 0x0, 1);
	i2c_write_codec(AIC3106_P0R18, 0x0, 1);
	i2c_write_codec(AIC3106_P0R19, 0x04, 1);
	i2c_write_codec(AIC3106_P0R20, 0x78, 1);
	i2c_write_codec(AIC3106_P0R21, 0x0, 1);	
	i2c_write_codec(AIC3106_P0R22, 0x04, 1);
	i2c_write_codec(AIC3106_P0R23, 0x78, 1);	
	i2c_write_codec(AIC3106_P0R24, 0x0, 1);
	
	i2c_write_codec(AIC3106_P0R37, 0xe0, 1);	
	i2c_write_codec(AIC3106_P0R38, 0x20, 1);

	i2c_write_codec(AIC3106_P0R43, 0x0, 1);	
	i2c_write_codec(AIC3106_P0R44, 0x0, 1);
	i2c_write_codec(AIC3106_P0R45, 0x0, 1);
	i2c_write_codec(AIC3106_P0R46, 0x0, 1);
	i2c_write_codec(AIC3106_P0R47, 0x80, 1);
	i2c_write_codec(AIC3106_P0R48, 0x0, 1);
	i2c_write_codec(AIC3106_P0R49, 0x0, 1);
	i2c_write_codec(AIC3106_P0R50, 0x80, 1);
	i2c_write_codec(AIC3106_P0R51, 0x0f, 1);

	i2c_write_codec(AIC3106_P0R61, 0x80, 1);
	i2c_write_codec(AIC3106_P0R62, 0x0, 1);
	i2c_write_codec(AIC3106_P0R63, 0x0, 1);
	i2c_write_codec(AIC3106_P0R64, 0x80, 1);
	i2c_write_codec(AIC3106_P0R65, 0x0f, 1);

	i2c_write_codec(AIC3106_P0R108, 0x11, 1);

	i2c_write_codec(AIC3106_P0R25, 0x80, 1);
	i2c_write_codec(AIC3106_P0R26, 0x8f, 1);
	i2c_write_codec(AIC3106_P0R27, 0x96, 1);
	
	aic3106_set_adc_channel();
	aic3106_set_agc_Cfg();
	aic3106_set_dac_channel();
	aic3106_set_output();
	aic3106_set_volume(0);
	aic3106_set_input_filter();


}
    HT3_RGMII_SDIO_USIM_I2S_20190612.pdf

  • 0 in reply to yangqin
    TI__Mastermind 22950 points

    Hello Qin,

    I had some time to look through the schematic and the register configs. Here are some questions/suggestions:

    1) All unused inputs should be tied together and shorted to GND using a .47uF capacitor.

    2) Why are MIC3R and MIC3L connected together and being sent to both left and right ADC's?

    3) In the register configs, I noticed that Line1L and Line1R are routed to the both the left and right ADCs and not being used. Why is this? This could be providing some unwanted noise. Again, I recommend following my first comment. 

    4) What is the FPGA doing with the DOUT data?

    As a sanity check, you are measuring DOUT and not DIN correct? Noise at DIN would imply the FPGA is providing the noise. 

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 30 points

    Hello Aaron,

    Under your suggestion, I made some modifications to the hardware and registers, but there will still be noise. I hope you can help me see if my understanding is correct. Here are some changes and questions and answers to your questions:

    (1) Under your suggestion, I made some modifications on the hardware circuit. Among the unused input pins, there are only test points or resistors on the 3, 5, 7, and 8 pins. So only these pins are connected and shorted to GND with a .47uF capacitor.

    (2) The person who designed the codec part of our company has already left, so I don't know why MIC3R and MIC3L are connected together and sent to the left and right ADC. Can you give us some suggestions on how to configure and connect MIC3R and MIC3L?

    (3) There will still be noise after I have shielded the two registers related to Line1L and Line1R and grounded them on the circuit.

    (4) During the loopback test, the FPGA board will send the data from DOUT to I2S. After receiving the data, I2S will send the data to the DIN of codec, and then you will hear what you said in the headset;

    (5) In our test, DIN is correct. When we play back a piece of data that confirms correctness and no noise, we can't hear the noise, and the data is correct.  So we think that noise is generated on the channel of DOUT.

    (6) I don't quite understand your sentence: "Noise at DIN would imply the FPGA is providing the noise." Can you tell me how this is judged? Thank you.

    Regards,

    Qin Yang

  • 0 in reply to yangqin
    TI__Mastermind 22950 points

    Hello Qin,

    Thanks for your reply. After reviewing the information you have provided a second time, I have some more questions/comments:

    1) Can you connect DOUT directly to DIN and see if this issue still occurs?

    2) I see that your BCLK is 400kHz in one capture and 417kHz in another. Your BCLK seems unstable.  

    3) Looking at your PLL configuration, I am assuming you are supplying an MCLK of 24.576MHz. Is this correct? If so, the PLL constraints are being exceeded. I would change P to a 2 and J to an 8 to meet the constraints described int the data sheet. 

    Regards,

    Aaron