Hello,
We are running test trying to determinate DC bias on each ADC. test set up
Fmaster clock 12.8MHZ
Sampling rate 10KHZ
2 channel I2S 16 bit
PGA disable
Line/mic inputs disable
we are seeing relativity large variance in DC bias between two ADC channels, sometimes up to 8 bit ie ADC CH0 DC bias is around +127 and second channel ADC around -128
Could you please advise what is acceptable dc bias offset from 0 and what is acceptable asymmetry between two ADC in same chip?
Thank you,