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TLV320AIC3105: Analog Bypass Mode
Part Number: TLV320AIC3105
My customer is considering to use TLV320AIC3105 in their system.There are three audio paths which they think as follow,
Normal Operation Mode: Case-1: Red solid line and Blue solid line Analog input signals of (a) and (b) are processed with digital effect, and are outputted.
Case-2: Red dotted line and Blue dotted line Analog input signals of (a) and (b) are converted to digital data, and are outputted through DOUT.
Digital Audio Input Mode from External Equipment: Case-3: Green dotted line and Orange dotted line Digital input signals of (c) and (d) from external equipment are outputted.
TLV320AIC3105 Audio Path.xlsx
Q1: As case-1, Is it possible that analog input signals of (a) and (b) are processed with ADC, digital effect and DAC, and are outputted.? Datasheet, page 80, "Table 105. Page 0/Register 107: New Programmable ADC Digital Path and I2C Bus Condition Register", shows When D3 is set to "1b", The programmable filter is connected to ADC output, if both DACs are powered down. From the above description, it is impossible otherwise DACs are powered down. If D3="1b" and DACs are powered up, what happens?
Q2: Digital microphone and analog microphone are in description of D5-D4 of "Table 105. Page 0/Register 107: New Programmable ADC Digital Path and I2C Bus Condition Register". What are digital microphone and analog microphone?
Q3: Default coefficients are in description of D7 and D6 of D5-D4 of "Table 105. Page 0/Register 107: New Programmable ADC Digital Path and I2C Bus Condition Register". What are default coefficients?
Q4: What is the relationship between, Setting of D7-to-D2 of "Table 17. Page 0/Register 12: Audio Codec Digital Filter Control Register" and Coefficients of ADC High-Pass Filter, "Table 165. Page 1/Register 65" to "Table 176. Page 1/Register 76" ?
Case 1 is not possible. The use of the DAC processing for the ADC is only possible if the DAC is powered down. There is no internal short from ADC to DAC, There is an analog PGA bypass, so the input to the ADC can be bypassed to the outputs before it is converted.... but once it is converted, the only way to send the ADC data to the DAC is to have the processor loop it back. I've attached a screen capture from a more recent block diagram for the AIC3104. This shows the functional behavior of SW-D1 and SW-D2
There is a logical AND condition. Where register 107 must be programmed to have the ADC digital path route to the DAC processing, AND the DAC must be powered down, else the DAC processing will be used for the DATA on DIN.
Case2 is fine.
Q1 - see above.
Q2. - this is a datasheet error. The AIC3105 is an optimized version of the AIC3106 which is in a 48pin QFN package, with a 32pin package there are no GPIOs and therefore no interface for the Digital mics. On the AIC3106, this register would select the input to the ADC decimation filters. (DMIC via GPIO or ADC)
Q3. - The default for register 107 is 0x30.
Q4 - Register 12 should be set to enable HPF. any of the 3 options is fine. once D6-7 of register 107 is enabled, the coefficients on page 1 become active.
is that clear?
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In reply to Steve-Wilson:
About Q1: They understood that Case-1 was not possible. They are considering the following Case-3 instead of Case-1. Could you check if it is possible? - Case-3: Analog input signals of (1) Red solid line and Blue solid line are proceeded with ADC, and are outputted to external equipment through DOUT once. Digital input signals from the external equipment to DIN of (2) Red solid line and Blue solid line are processed with digital effect, and are outputted through DAC.
TLV320AIC3105 Audio Path Case-3.xlsx
About Q3: When D7 and D6 of "Page 0 / Register 107" are set as "00b", Default coefficients are used when ADC high pass is enabled. Are the default coefficients Reset Value of "Page 1 / Register 1" to "page 1 / Register 76"?
About Q4: When "Page 0 / Register 12" is set to enable HPF, there are the 3 options and each option has "-3dB frequency" setting. On the other hand, there is equation (1) on page 25 which is the transfer function of the digital high-pass filter based on N0, N1 an D1 coefficients. Does the equation (1) also set the "-3dB frequency"? What is the relation between the above two settings?
In reply to Koshi Ninomiya:
Case 3 is no problem.
re Q3: the default coefficients are held in the device RAM and are not shown on page 1.
re Q4: as you said, Equation 1 Is the transfer function for the filter, so of course it controls the output of the filter for a given input. TI does provide tools to create filters such as the TLV320AIC3105evm GUI or TIBQ. there are other methods for creating filters such as Matlab, but when using matlab there are additional steps for converting to the format the TI codec is expecting.
About Q3: When D7 and D6 of "Page 0 / Register 107" are set as "00b", Could you let me know the default coefficients for ADC High Pass which are held in the device RAM?
This is not accessible to customers, this is an old codec, while we have design support for it, this seems like a trivial inquiry, and our design team is very busy. You know the response of the preset filters. What is the purpose of knowing this?
TLV320AIC3105 datasheet shows "Default coefficients are used", the customer wants to understand the default coefficients.
The default coefficients are the ones referenced in register 12 (digital filter control register)
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