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TLV320AIC23B: regarding TLV320AIC23B’s Analog-line-input-2-line-output bypass mode THD under AVDD=2.7V

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Part Number: TLV320AIC23B

Topic: Audio CODEC, regarding TLV320AIC23B’s Analog-line-input-2-line-output bypass mode THD under AVDD=2.7V

TI FAE:

Sir/Madam:

May I consult you one thing regarding TLV320AIC23B audio codec’s THD under AVDD=2.7V for Analog Linein to Lineout, bypass mode?

Copy below is the table from TLV320AIC23B datasheet: (pls see attachment)

2.3.3 Analog Line Input to Line Output (Bypass)

In bypass mode, analog linein to analog lineout, AVDD=2.7V, test conditions are shown below:

Input analog signal freq=1kHz, 0dB for signal level.

If we treat 0dB amplitude as the output level, that means the output level should be equal to 1.0Vrms.

However, under the condition of AVDD=2.7V, the output of 1.0Vrms means 2.828Vpp (Peak2Peak Value).

That means the analog output level is even higher than AVDD=2.7V.

As a result, a serious distortion would happen under the output level of 2.828Vpp.

Because the nonlinear region of the chip is reached due to over large amplitude for the output level.

Under such condition, typical value of -86dB reading is unbelievable! (According to the Table 2.3.3, it’s -86dB)

Please see the bypass mode condition in red rectangle for the table 2.3.3 shown above.

 

To confirm this, we use TLV320AIC23EVM2 bench board to test TLV320AIC23B codec chip, with the register setting for bypass mode, and AVDD=2.7V, analog output level = 1Vrms, etc.. The result was quite bad, THD just around -24.5dB (not the value near -86dB). It proves what we concern for such conditions --- induced serious distortion due to over large amplitude.

Please see the AP analyzer result for EVM2 test below: Can we say this typical value is not correct indicated in the datasheet?

Regarding TLV320AIC23B Bypass Mode AVDD2.7V THD Value.docx

  • User, 

    This is an error in measurement.  

    As you can see the ADC full-scale input range is 1VRMS at AVDD=3.3V, but that is not the full-scale range at 2.7.  The full-scale range tracks linearly with AVDD.  The same is true of the DAC (see section 3.2.3 in the datasheet)  This means that your 0dB input when AVDD = 2.7V should match the full-scale input of the ADC at AVDD = 2.7V. Please try this and get back to me. 

    This Codec was designed nearly 20 years ago now, some of the quirks age better than others.  the vast majority of our codec portfolio has internal LDOs for the ADC/DAC supply,  which allows us to keep the reference (full-scale input/output voltage) constant across AVDD range.

    best regards,

    -Steve Wilson

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