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PCM4104: SCLK jitter specification / THD issue

Part Number: PCM4104

Hi Team,

We have a THD issue on our design, and we are trying to resolve it.

Our THD is 10 dB above the specification @0dBFs as you can see in attached files.

So we have some qustions:

1) The Jitter on MCLK is specified at 100psRMS or less . Is it wideband, baseband or periodic jitter ?

2) The reference design has been followed with the right decoupling capacitors and the layout is pretty good. Do you have an idea of what could be causing the issue ? Is it more the jitter, the layout or the power supply?

3) How the jitter on MCLK impact the THD ? Do you have an application note ?

Thanks

  • Hi Arnaud,

    The noise would likely be coupled by the power supply.  These devices used a simple resistor divider for a reference, so there is little attenuation of the noise accept for the caps on the reference pins.

    Moreover, I think we might have a measurement issue with your data.  Can you share your schematic? What is your sample rate? What is the input filter you are using on the instrument? We only specify the device with a brickwall low-pass filter at 20kHz.

    Thanks,

    Paul

  • Hi Paul,


    Our measurements have been done with A-weighted and a Low pass filter at 20KHz and we are 48Khz.Also, we have done it at 96K and 192K.

    I can share our schematic and provide you more pictures but is it possible to continue in private?

    Also, do you have an answer on my first question?


    Thanks
    Arnaud

  • Hi Arnaud,

    Please share you schematic with me at frost@ti.com.  I, unfortunately, do not have any jitter information for this device, but seeing as the THD is flat at very low amplitude, I think you are noise limited. We can try to do the noise calculation once you send the schematic.

    Thanks,

    Paul