Hi Team,
We have a THD issue on our design, and we are trying to resolve it.
Our THD is 10 dB above the specification @0dBFs as you can see in attached files.
So we have some qustions:
1) The Jitter on MCLK is specified at 100psRMS or less . Is it wideband, baseband or periodic jitter ?
2) The reference design has been followed with the right decoupling capacitors and the layout is pretty good. Do you have an idea of what could be causing the issue ? Is it more the jitter, the layout or the power supply?
3) How the jitter on MCLK impact the THD ? Do you have an application note ?
Thanks