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PCM3500: SYNCHRONIZATION REQUIREMENTS

K.Yaita
Guru 29690 points
Part Number: PCM3500

Hi Team,

The datasheet shows the following about the condition of detecting a loss of synchronization.
However I couldn't catch the content (yellow part) cleary.
-----------------------------------------------
SYNCHRONIZATION REQUIREMENTS
The PCM3500 requires that FS and BCK be synchronous with the system clock. Internal circuitry is included to detect
a loss of synchronization between FS and the system clock input. If the phase relationship between FS and the system
clock varies more than ± 1.5 BCK periods, the PCM3500 will detect a loss of synchronization. Upon detection, the
DAC output is forced to 0.5VCC and the DOUT pin is forced to a high impedance state. This occurs within one sampling
clock (FS) period of initial detection. Figure 10 shows the loss of synchronization operation and the DAC and ADC
output delays associated with it.
-----------------------------------------------

Does PCM3500 count BCK in 1/fs?
Could you let us know how to confirm the loss of synchronization is occured or not in actual BCK, FS, system clock wave form (timing chart)?

Best Regards,
Yaita

  • 0
    TI__Mastermind 30030 points

    Yaita, 

    This simply means that the BCk,FS and SCKIO should all be derived from the clock.  

    Figure 10 shows the functionality.  

    The loss of synchronization will cause some undefined data,  but this will get cut off within 1/fs.  If could be less than that depending upon where in the sample the clocks became out of sync. 

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    Guru 29690 points

    Hi Steve-san,

    Thank you for your support.

    I would like to know the detail condition that PCM3500 can detect loss of synchronization. 
    Is the following condition correct?
    - PCM3500 detects loss of synchronization if FS and BCK isn't synchronous with the system clock
    - PCM3500 detects loss of synchronization if there is more than ±1.5 BCK in 1/fs (less than 14.5 BCKs or more than 17.5 BCKs in 1/fs)

    Best Regards,
    Yaita

  • 0 in reply to K.Yaita
    TI__Guru**** 168605 points

    Hi Yaita,

    Sorry for the delay here.  The synchronization depends on the relationship of the BCK period to FS width.  Loss of synchronization could occur in the first case above.  The width of the frame sync pulse is normally 1 BCK wide, which is 32 periods of the system clock. In the second condition above, if FS is synchronous to BCK, and there are more (or less) than 16 BCK between FS pulses, I would expect you would have a corrupted data transfer rather than a loss of synchronization.  This should not be an issue when running in Master mode.