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Part Number: TLV320AIC23B
I am working on a project containing tms320vc5410 and the tlv320aic23b codec.
We have a bug with our DSP software.
Right after power up the first control word transmitting by the
DSP contains 15 clocks instead of 16 (Mcbsp operating in SPI mode).
The chip select of the codec rising edge comes after 15 clocks.
The next control words are fine.Because of that the codec is configured wrongly.
My questions .
Is the shift register in the codec receiving the control data stream has a determined value after powerup?
so I can to figure out what would be the data latched from the shift register (after receiving only 15 bits ) ?
While the TLV320AIC23B is still a good device, it is edging on 20 years old and we'll need to leverage the information in the datasheet. In this case the datasheet says the data bits are latched after the /CS rises following the 16 SCLK clock edges.
Since the device may not receive all 16 clocks it sounds possible that the register write may not get latched. Could you consider writing the 1st register a second time so the 2nd write will have all 16 clocks?
Regards,Collin WellsPrecision ADC Applications
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