Hello. Team
I'm struggling to configure TLV320ADC3140 as Audio Bus Master.
And I would like to use this functional mode. (Auto Clock Generation with Internal PLL enabled)
In case of my board, 24.576MHz OSC4 is connected to GPIO1 for MCLK
And IN1P_GPI1 will be used for D-MIC data and INIP_GPO1 is going to be used for D-MIC clock.
Anyway, when I just check BCLK/FSYNC/INIP_GPO1 for D-MIC clock based on 24.576MHz MCLK, I can't see any signal coming out.
Could you let me know what I am missing to configure TLV320ADC3140 as Audio Bus Master?
Here is my register value.
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root@euto-v9:~# i2cdump -f -y 7 0x4c
No size specified (using byte-data access)
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 00 00 81 00 00 05 00 70 00 00 00 00 01 02 03 04 ..?..?.p....????
10: 05 06 07 80 48 ff 10 10 04 20 02 08 00 00 02 40 ????H.??? ??..?@
20: 00 a0 40 40 00 00 00 00 00 00 00 44 00 00 00 00 .?@@.......D....
30: 00 00 00 ff 00 00 00 00 80 00 00 00 00 00 c9 80 ........?.....??
40: 00 00 00 c9 80 00 00 00 c9 80 00 00 00 c9 80 00 ...??...??...??.
50: 00 00 c9 80 00 00 00 c9 80 00 00 00 c9 80 00 00 ..??...??...??..
60: 00 c9 80 00 00 00 00 00 00 00 00 01 40 7b 00 00 .??........?@{..
70: e7 00 00 00 00 00 00 c0 00 00 ff 00 ff 8c 79 00 ?......?.....?y.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
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Thank you.
Kyungwon