Hi All:
I want configure PCM5242 in software mode / 3-wired (BCK+LRCK+DATA) due to EMI issue. (Need remove MCK to reduce EMI)
Reference spec: http://www.ti.com/lit/ds/symlink/pcm5242.pdf?&ts=1590142233192
Table 50 shows a recommend clock divider setting for PLL. When the fs = 48kHz the value of P=1 / J=16 / D=0 / R=2
All registers I set for PLL are:
1. Register 4 = 0x01, (PLL enable)
2. Register 13 = 0x02, (Choose BCK for PLL)
3. Register 14 = 0x10, (Use PLL clock for DAC)
4. Register 20 = 0x00, (P=1)
5. Register 21 = 0x10, (J=16)
6. Register 22 = 0x00, (D=0)
7. Register 23 = 0x00, (D=0)
8. Register 24 = 0x01, (R=2)
9. Register 27 = 0x01, (NMAC = 2)
10. Register 28 = 0x0F, (NDAC = 16)
11. Register 29 = 0x03, (NCP = 4)
12. Register 30 = 0x07, (DOSR = 8)
13. Register 37 = 0x02, (Disable clock auto detection)
But, still can't hear sound output from analog output, is there anything wrong?
Please advise. Thanks