TLV320AIC3204: Using the ADC portion of the AIC3204 at 192kSps with filter B

Here are the register configurations (see below).  This is straight from the TMDX5535EZDSP example code.  I just changed the gain registers some and the AOSR (from 0x80 to 0x20 - which should change the sample rate) and altered the Signal Processing Blocks to be Filter B (via selection of PRB_R7 for page 0 , register 61).  It passes the audio nice and strong and is really quite good.  The only problem is that it is not supposed to be at 48kHz sample rate (if I have the AOSR at 0x80, it is 48kSps and if I change it to 0x20, it is still 48 kSps - this is not how the documentation says it should work).  This is all assuming I am not missing something, which I might be.

Can someone please tell me what I am doing wrong? or

Please can someone give me a definitive answer that this does not work with this chip?

/* Configure AIC3204 */
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 1, 0x01 ); // Reset codec
EZDSP5535_waitusec(1000); // Wait 1ms after reset
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 1, 0x08 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 0x01 ); // Enable Analog Blocks, use LDO power
AIC3204_rset( 123,0x05 ); // Force reference to power up in 40ms
EZDSP5535_waitusec(50000); // Wait at least 40ms
AIC3204_rset( 0, 0x00 ); // Select page 0

/* PLL and Clocks config and Power Up */
AIC3204_rset( 27, 0x0d ); // BCLK and WCLK are set as o/p; AIC3204(Master)
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 0x03 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 0x07 ); // PLL setting: J=7
AIC3204_rset( 7, 0x06 ); // PLL setting: HI_BYTE(D=1680)
AIC3204_rset( 8, 0x90 ); // PLL setting: LO_BYTE(D=1680)
AIC3204_rset( 30, 0x88 ); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, 0x91 ); // PLL setting: Power up PLL, P=1 and R=1
EZDSP5535_waitusec(10000); // Wait for PLL to come up
AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
//AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to
AIC3204_rset( 20, 0x20 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6 //
AIC3204_rset( 61, 7 ); // Selecting PRB_R7 path // 
//AIC3204_rset( 83, 20 ); //  Increase Gain on Left // 
AIC3204_rset( 84, 20 ); // Increase Gain on Right // 
AIC3204_rset( 11, 0x82 ); // Power up NDAC and set NDAC value to 2
AIC3204_rset( 12, 0x87 ); // Power up MDAC and set MDAC value to 7
AIC3204_rset( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2

/* DAC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 16, 0x00 ); // Unmute HPL , 0dB gain
AIC3204_rset( 17, 0x00 ); // Unmute HPR , 0dB gain
AIC3204_rset( 9 , 0x30 ); // Power up HPL,HPR
EZDSP5535_waitusec(100 ); // Wait

/* ADC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 52, 0x30 ); // STEREO 1 Jack
// IN2_L to LADC_P through 40 kohm
AIC3204_rset( 55, 0x30 ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 57, 0xc0 ); // CM_1 (common mode) to RADC_M through 40 kohm
AIC3204_rset( 59, 0x00 ); // MIC_PGA_L unmute
AIC3204_rset( 60, 70 ); // MIC_PGA_R unmute // gain
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC
AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC
AIC3204_rset( 0, 0x00 ); // Select page 0

EZDSP5535_waitusec(100 ); // Wait

Greg, 

My understanding is due that the processing block will force the AOSR=64 value.  For processing block A,  you could set to 64 or 128 but only 64 or 128.  

I can check with our design team for more details, but I do not believe the AIC3204 can do this. 

best regards,

-Steve Wilson

Thanks for your feedback!

I had just seen online where someone had selected filter B with 192kHz sample rate (which is what I want to do).  My AOSR seems to not have any effect at all when I change it.  I was able to get the 192kHz sample rate with filter B by changing the J parameter and playing with the others.  However, it looks pretty bad.  It has a high frequency hum riding on my test tone. This is with a 2kHz input from a signal generator.  You can notice the sampling rate is truly 192kHz and register 61 on page 0 is set to 7 (filter B):

Time-FreqPlot.docx

However, I am still waiting on a definitive answer on the subject of course (while continuing to see if there is anything further I can do to make it work correctly).

Thank you so much for the clarification.  I think the plot I saw previously was just a frequency response curve, which looked ok, which I Was able to replicate.  However, the underlying spurious free dynamic range was bad for the reasons you mentioned.

Your post resolved my issue.

You're welcome Greg, Its unfortunate that there isn't a simple work around.  if you're looking for an audio ADC that can do this, My understanding is that the PCM186x series have a passband of 0.454*Fs even for 192khz. I would need to double check that as the datasheet is a little vague.

best regards, 

-Steve Wilson