Hi!
I have a working setup of TLV320AIC3262 sampling analog audio signal at 32khz sample rate. Signal is then output to I2S interface at the same sample rate and processed by the host CPU.
I'm struggling to change the sampling rate to 192 khz which is a requirement of my project. I have updated clock configuration, changed framework to AIC3262App2x1x and I/O components to Dec1xIn, Int2xOut. I managed to get proper I2S output rate, but I'm getting only noise. What can be a reason for that?
Here is a sample from my config:
reg[0][0][1] = 0x01 ; reg(0)(1)(0x00 => 0 ) S/W Reset reg[0][0][4] = 0x33 ; ADC_CLKIN = PLL_MCLK, DAC_CLKIN = PLL_MCLK reg[0][0][5] = 0x00 ; PLL_CLKIN = MCLK1 reg[0][0][6] = 0x91 ; P=1, R=1 reg[0][0][7] = 0x18 ; P=1, R=1, J=24, D=576 reg[0][0][8] = 0x40 reg[0][0][9] = 0x02 reg[0][0][13] = 0x01 ; DOSR = 384 (MSB) reg[0][0][14] = 0x80 ; DOSR = 384 (LSB) reg[0][0][18] = 0x82 ; NADC Powerup NADC = 2 reg[0][0][19] = 0x88 ; MADC Powerup MADC = 8 %%if (%%prop(SampleRate) == 192000) reg[0][0][20] = 0x20 ; AOSR = 32 %%endif %%if (%%prop(SynchMode) == 1) reg[0][0][11] = 0x02 ; NDAC = 2, divider powered off %%else reg[0][0][11] = 0x82 ; NDAC = 2, divider powered on %%endif reg[0][0][12] = 0x88 ; reg(0)(0)(0x0c => 12) DAC Powerup MDAC = 8 reg[120][0][50] = 0x88 ; Interpolation Ratio is 8, FIFO = Enabled reg[100][0][50] = 0xa4 ; Decimation Ratio is 4, CIC AutoNorm = Enabled, FIFO = Enabled ...
Tomek