PCM9211: Trigger of UNLOCK error

Hi Kazuki,

The DIR PLL will unlock if the input signal is not valid. This could occur if the input is missing or outside of the supported frequency range. It can also happen if there are glitches on the input that cause the PLL to miss some clock edges. Although the PCM9211 does have the ability to detect non-PCM data, the data still has to be formatted such that a clock can be adequately recovered.

Best,

Zak

Hi Zak,

Thank you for your prompt reply.

I'd like to confirm the behavior under following 2 specific case.
Would you tell me the unlock error's behavior?

1.When audio signal is changed, it may cause the change of cycle of preamble. So I think this case cause of unlock error. Then I'd like to know about when release the this unlock error.

2. When channel status and actual S/PDIF fs are contradicted, Do this case notify unlock error? (I guess customer concern about the case of changing input data to that have different input.)

Best regards,
Kazuki Kuramcohi

Hi Kazuki,

I think this partially depends on how your system is set up. If when changing audio on a given input you still maintain a continuous data-stream and once you enable the audio it synchronizes to the S/PDIF bit stream then the PLL won't lose lock. For example, when you test with an Audio Precision and use an optical connector the AP outputs a standard bit stream for clock recovery regardless of whether the digital output is active. So even though there is no valid audio data, the PLL maintains lock because the clock signal is still provided. 

If you ever MUX the input pins or interrupt the S/PDIF stream, the PLL will lose lock and have to relock to the new audio source. The time it takes to do this varies, but it is typically around 15ms with a maximum of 100ms. However as stated in the datasheet: "PLL lock-up time varies with ERROR release wait time setting (Register 23h/ERRWT)." 

Best,

Zak

Hi Zak,

My understanding is that it will mute the output If S/PDIF stream is switched instantly but abnormal data stream is putted at once. Is this right?
Also I think it will mute the output as well if Channel status and actual S/PDIF stream are inconsistent. Is this correct?

Best regards,
Kazuki Kuramochi

Hi Kazuki,

I'm not sure I understand your question as you have phrased it, but I will reiterate that ANY disturbance of the input, whether it's a glitch, muxing to a different channel, change in sample rate, or anything else that changes the clock rate at the input will result in the PLL losing lock until it re-synchronizes to the clock edge. If by the channel status and actual S/PDIF stream being inconsistent, you mean that a change to the input has occurred, then yes the device will mute.

Best,

Zak

Zak-san,

Sorry for making your confusion.

I'd like to confirm about the case of  that S/PDIF signal is interrupted but signal is inputted seamlessly.
For example, input signal is interrupted in the middle of audio sample ward but input signal is switched immediately. So In this case, data format is abnormal(including preamble cycle) but data stream is persist.
I think this case is don't assert unlock error if sample rate isn't change.
Also I think pll is based on data stream(including Sync preamble, Aux, audio sample word and VUCP data). So PLL continuously lock the clock as long as S/PDIF signal is inputted even if input signal's format is not correct.
Is this correct? Or you think this case is glitch?

Best regards,
Kazuki Kuramochi

Hi Kazuki-san,

Thank you for the clarification, I think I understand now. As long as the S/PDIF stream is constant, then the PLL shouldn't lose lock, even if there is temporarily no valid audio content in the stream or the format has changed. However, it is likely in this case that you will generate another kind of error depending on the nature of your signal.

There are several allowable error sources from the DIR: Change of incoming S/PDIF sample frequency (Register 25h / EFSCHG), Out-of-range incoming S/PDIF signal (Register 25h / EFSLMT), Non-PCM data (Register 25h / ENPCM), Data invalid flag is the stream (Validity bit = 1) (Register 25h / EVALID), Parity error (Register 25h / EPARITY), and PLL unlock (default) (Register 25h / EUNLOCK)

Best,

Zak

Hi Zak-san,

I appreciate your dedicated support.

You mostly resolved my question.
And then I'd like to make sure about the behavior of PCM9211 for S/PDIF input just in case.

My understanding is PLL unlock error is not detected by no vaild S/PDIF stream as long as following datasheet's sample frequency as below. requirement. And this no valid stream is not detected as Non PCM and Parity error.

Is this correct?

Best regards,
Kazuki Kuramochi

Hi Zak-san,

Sorry for being pedantic but would you answer my question?


Best regards,
Kazuki Kuramochi

Hi Kazuki-san,

I still don't understand what case you are considering that doesn't fall under what we have already discussed. If you've followed the datasheet's biphase sampling requirements and there aren't any glitches in the stream, then it is a valid S/PDIF stream. I think the best thing for you to do would be to acquire a PCM9211 EVM and test the behavior with the signal you have in mind as this would dispel any doubts you or your customer might have.

Best,

Zak

Zak-san,

I think I need to confirm about the meaning of glitch.
Would you explain about the meaning of glitch?
I'd like to know about the the definition of trigger of causing PLL unlock error.

Best regards?
Kazuki Kuramochi?

Zak-san,

Would you provide the detailed meaning of your "glitch".


Best regards,
Kazuki Kuramochi

Hi Zak-san,

I apologize you regarding my late response. 

I understood overview of trigger of causing clock error.
However I want to know about actual trigger of error as following.
・As for bi-phase encoding error, does it cause unlock error if your explained situation is happened just at once?
For example, detect 3 times high or low data at once,  detect abnormal sub frame that have longer or shorter bit length than 32 bit...
・In regard to preamble signal, does it cause unlock error if that it miss the preamble signal just at once? or is there threshold of repeatedly missing preamble?

Best regards,
Kazuki Kuramochi