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Part Number: TLV320ADC5140
Our customer is having some glitches on the MCLK signal of TLV320ADC5140. She does not know if it's acceptable or not since no electrical characteristic for MCLK was provided on the datasheet.
She wonder if the glitch on MCLK can be introduced by using an active probe? MCLK runs on relatively low frequency, And with passive 10Mohm/11pF, she don't see any issue.
If you have information about how to clear this glitch, it would be highly appreciated.
Thanks in advance!
The MCLK input signal needs to run at rough 50% duty cycle with a maximum frequency of 36.864MHz. Glitches on the line that are logic levels are not acceptable and should be eliminated. The glitches are likely a result of coupling between two signals running adjacent to eachother or possibly a power-supply/GND disturbance in the system. The fact that a small shunt capacitance to GND (scope 11pF) gets rid of the glitch, further confirms it's likely a coupling issue.
Regards,Collin WellsPrecision ADC Applications
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In reply to Collin Wells:
Updates are as following:
1.) Duty-Cycle min/max is 45% and 55% respectively
2.) Jitter should be <1ns if the PLL will be used with the MCLK as an input
3.) Logic level glitches must be avoided. The glitches may trigger a clock error which will shut down the ASI. Please mitigate the glitches by adding some series resistance near the output drivers, avoiding long adjacent trace routing without GND separation, and possibly adding some shunt capacitance as found in the debug.
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