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[FAQ] TLV320ADC5140: MCLK Input Clock Requirements

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Part Number: TLV320ADC5140

Hello, 

What are the requirements for the MCLK clock signal input to the TLV320ADC5140, TLV320ADC3140, and TLV320ADC6140 when operating as an Audio master with an external MCLK input?

Regards,
Collin Wells
Precision ADC Applications

  • 1.) The maximum input frequency is:  36.864MHz.

    2.)  Duty-Cycle min/max is 45% and 55% respectively

    3.)  Jitter should be <1ns if the PLL will be used with the MCLK as an input

    4.)  Logic level glitches or other noise on the clock input must be avoided.  Glitches may trigger a clock error which will shut down the ASI.  Please keep the MCLK input signal as clean as possible by adding some series resistance (10-33 Ohms) near the output drivers, avoiding long adjacent trace routing with other switching signals, and possibly adding some shunt capacitance if the glitches are sourced extrinsically. 

    Regards,
    Collin Wells
    Precision ADC Applications

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