TAS6424-Q1: Rise and Fall Time of clock signal

Josef Warta

Part Number: TAS6424-Q1

Hello Team,

we need clarification regarding rise and fall time of FSYNC and DATA. Is the value in our datasheet also valid for FSYNC and DATA? Or only for BCLK.
My customer is using MCLK with 256xFS (12.288MHz). Currently they stretch this maximum value of 4ns at FSYNC to 4.5ns. Is this still acceptable? Because this would help to improve EMI issues.

Many Thanks

Josef

over 3 years ago

0 Gregg Scott over 3 years ago

TI__Mastermind 34235 points

Hi Josef,

I had to do some research and this specification should be 4ns as a maximum and not a minimum. If they choose to slow down the rise and fall time to 4.5ns, there could be a noise penalty in the audio output.

0 Andreas Walter1 over 3 years ago in reply to Gregg Scott

Prodigy 10 points

Hello Mr. Scott,

thanks for your feedback. This means we need to be below this 4ns as well for the FSYNC and the DATA line? For BCLK this limits makes definetly sense and here I undestand that a violation could cause a noise issue.

I expect the rise/fall times are calculated between 30%Vdd and 70%Vdd. Is this correct?

Thanks in advance

Andreas

0 Gregg Scott over 3 years ago in reply to Andreas Walter1

TI__Mastermind 34235 points

Andreas,

I missed this reply, I am sorry as I was on vacation. You are correct.

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TAS6424-Q1: Rise and Fall Time of clock signal