Hello Sir,
One of my customers connects TLV320ADC5140 EVM to their own board. They uses 4-CH single-ended input. FSYNC is 32KHz, MCLK is 8.192MHz, SBCLK is 4.096MHz, the SBCLK/FSYNC is 128. The power up order is: Platform, AVDD, IOVDD and after they are stable, the CLK starts, then SHDNZ is driven to high level, after 10ms, REGISTER is set up with using PPC3. SBCLK and FSYNC works well. While the noise can be heard clearly and original input signal can be heard as well behind the noise.
I thought this might cause by unjustified filters setting-up (decimation filter, HFP and Bi-quad filter). What and how do I need to check?
Thanks for your information!
Register setting-up:
// Page 0
{ 0x00, 0x00 },
// Book 0
{ 0x7f, 0x00 },
// Page 0
{ 0x00, 0x00 },
// Reset Device
{ 0x01, 0x01 },
// 1mS Delay
{ CFG_META_DELAY, 0x01 },
//
---------------------------------------------------------------------------
--
// Begin Device Memory
//
---------------------------------------------------------------------------
--
// Book 0 Page 0 (0x00) Dump
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x00 },
{ 0x02, 0x81 },
{ CFG_META_DELAY, 0x01 },
{ 0x07, 0x30 },//0x30 32bit 0x20 24bit
{ 0x14, 0x36 },//add 32k 128 ratio
{ 0x21, 0x21 },
{ 0x3b, 0x60 },
{ 0x3c, 0xa1 },
{ 0x41, 0xa1 },
{ 0x46, 0xa1 },
{ 0x4b, 0xa1 },
{ 0x6b, 0x00 },
{ 0x6c, 0x02 },//AGC SELECT
{ 0x6d, 0x9b },
{ 0x74, 0xf0 },
#if 1
// Page 1 (0x01) Dump
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x01 },
{ 0x05, 0x01 },
{ 0x07, 0x20 },
// Page 4 (0x04) Dump
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x04 },
{ 0x49, 0xe6 },
{ 0x4a, 0x48 },
{ 0x4b, 0xc6 },
{ 0x4c, 0x80 },
{ 0x4d, 0x19 },
{ 0x4e, 0xb7 },
{ 0x4f, 0x3a },
{ 0x50, 0x7f },
{ 0x51, 0xcc },
{ 0x52, 0x91 },
{ 0x53, 0x8b },
{ 0x54, 0x24 },
{ 0x55, 0x46 },
{ 0x56, 0xc8 },
{ 0x57, 0x84 },
{ 0x58, 0x04 },
{ 0x5c, 0x04 },
{ 0x60, 0x04 },
{ 0x64, 0x04 },
{ 0x68, 0x04 },
{ 0x6c, 0x04 },
{ 0x70, 0x04 },
{ 0x74, 0x04 },
{ 0x78, 0x04 },
{ 0x79, 0x9e },
{ 0x7a, 0x7f },
{ 0x7b, 0x30 },
{ 0x7c, 0x04 },
{ 0x7d, 0x9e },
{ 0x7e, 0x7f },
{ 0x7f, 0x30 },
// Page 6 (0x06) Dump
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x06 },
{ 0x1d, 0x04 },
{ 0x1e, 0xb0 },
#endif
// Power up/down register
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x00 },
{ 0x75, 0x60 },