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[FAQ] TLV320ADC5140: What are the power-up time and power-down times for different sampling rates?

Intellectual 2835 points

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Part Number: TLV320ADC5140

Hi. What are the power-up and power-down times for different sampling rates for the TLV320ADCx140 family? That family includes the following devices: TLV320ADC5140TLV320ADC6140TLV320ADC3140.

  • The power-up time (the time it takes for the part to go from “sleep mode” to “active mode”) for the TLV320ADCx140 family is comprised of this formula:

    Power-up time = buffer time (dependent on quick-charge setting) + soft-stepping time (dependent on sampling rate)

    The “buffer time” is dependent on the quick-charge setting (refer to note below), but under default conditions it is approximately 12.3ms and this can vary +/- 10%. This includes power-up of AREG, VREF, PLL, ADC modulator, internal digital before we start sending un-muted record data to ASI bus.

    The “soft-stepping time” is 0 ms if it is disabled. If it is enabled, then it is based on the sample rate with 0.5dB step per frame (from -100dB to programmed digital volume control setting). For example, for 192kHz sample rate and a volume control setting = 0dB, then it will be 175/Fs = 0.9ms.

    Note the ASI data is held inactive until the circuitry used to help quick-charge the external AC coupling has completed. The INCAP QCHG register settings allow for different quick-charge timings and the setting will dictate the time it takes for data to begin streaming out. This operation helps the system level-stabilization occur quickly and is to prevent erroneous data at the output during this coupling capacitor charging time, though it delays when the ASI data begins coming out.

    Note changing the INCAP quick charge setting (can be done by writing to the SHDN_CFG register, refer to Figure 1 below) will impact when data will start streaming and therefore the buffer time. Refer to Figure 2 below with the default quick charge setting of 2.5ms. This plot shows roughly how long it takes AREG to power up (approximately 1.4ms), the PLL to power up and lock (approximately 8.1ms), and for data to be output on the bus (approximately 11.9ms total, including quick charge time). This is in line with the expectations of a 12.3ms startup time +/- 10%. Figure 3 is the same plot but with a quick charge setting of 12.5ms. From the plot it is clear there is a 10ms delay in the output data streaming between the 2.5ms (default) and 12.5ms quick charge setting. This would increase buffer time from 12.3ms to 22.3ms. Another thing to consider is the soft ramp. This does not gate the data output, but does add additional delay before the data output reaches the programmed volume. It can be disabled if desired. This testing was done with the device configured as the ASI bus master with data captured by triggering off of the I2C command to initiate a device wakeup. The device was generating the clocks, which is why PLL startup and lock time can be approximated from the capture.

     

    Figure 1: Write to the SHDN_CFG register to adjust the quick charge settings.

     

    Figure 2: Capture to show DOUT when a default quick charge setting of 2.5ms is used.

     

    Figure 3: Capture to show DOUT when a quick charge setting of 12.5ms is used.

     

     

    The power-down time (the time it takes for the part to go from “active mode” to “sleep mode”) for the TLV320ADCx140 family is dependent on sample rate. Table 1 shows which power-down times correspond to which sampling rate intervals.

    Sample Rate (kHz)

    7.35 – 14.7

    14.7 - 44.1

    44.1 - 48

    88.2 - 768

    Power-Down Time (ms)

    25

    15

    5.2

    2.7

    Table 1: Power-down times for each sampling rate interval.

    Soft-stepping can be enabled or disabled and occurs in parallel with power-down time. If soft-stepping is enabled, it scales dependent on sampling rate by 175/fs. Table 2 below shows how soft-stepping times scale with sampling rate.

    Sample Rate (kHz)

    7.35

    8

    14.7

    16

    22.05

    24

    29.4

    32

    44.1

    Calculated Soft-Step Time (ms)

    23.810

    21.875

    11.905

    10.938

    7.937

    7.292

    5.952

    5.469

    3.968

    Measured Soft-Step Time (ms)

    24.48

    21.20

    12.56

    10.85

    8.06

    7.199

    6.41

    5.449

    4.18

     

    Sample Rate (kHz)

    48

    88.2

    96

    176.4

    192

    352.8

    384

    705.6

    768

    Calculated Soft-Step Time (ms)

    3.646

    1.984

    1.823

    0.992

    0.911

    0.496

    0.456

    0.248

    0.228

    Measured Soft-Step Time (ms)

    3.75

    2.16

    1.91

    0.187

    0.18

    0.121

    0.11

    0.087

    0.074

    Table 2: Power-down times and soft-stepping times for each sampling rate interval.

    Note the measurements in the tables are representative of typical data, it is normal to experience some deviation.

    Regardless of whether soft-stepping is enabled or disabled, there will be a 230uS delay for the data to stop outputting. This is independent of sampling rate.

    When soft-stepping is enabled, this time will be dependent on the sample rate (refer to table below), however the time it takes for a clean power down can still be inferred from Table 1.

    The DREG settings in the SHDN_CNFG register must be addressed as well.

    The first setting is to have DREG immediately power down following a shutdown, and this is shown in Figure 4 below. As the register states, this only applies to a toggle of the SHDNz pin. Putting the device into sleep mode by writing to register 0x02 does not power down DREG.

    Figure 4: Capture to show DREG powering down immediately after a shutdown.

     

    Another option is to keep DREG active until the device shuts down cleanly, and in this case the shutdown timing would be based on the sample rate as given in tables above. An example of this is shown in Figure 5 below with soft-stepping enabled, and again in Figure 6 below with soft stepping disabled operating at 8kHz.

    Figure 5: Capture to show DREG being kept active until device cleanly shuts down with soft-stepping enabled.

     

    Figure 6: Capture to show DREG being kept active until device cleanly shuts down with soft-stepping disabled.

     

    The last option is to program the timer in the SHDN_CNFG register to have the device power down after the timer expires. This only applies if the time it would take for the device to go through a clean shut down exceeds the timer. That is why the previous plots were tested with an 8kHz sample rate because this makes the effect of this timer clearly visible since it should take ~25ms to power down cleanly at 8kHz operation. This is shown in Figure 7 below with the timer set to 10ms. From the plot it is clear that it takes approximately 10ms to shut down now instead of 25ms.

    Figure 7: Capture to show the effect of the timer. In this case the timer is set 10ms, and DREG now takes approximately 10ms to shut down instead of 25ms.

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