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Original question:

TLV320DAC3100: TLV320DAC3100: Interfacing TLV320DAC3100 with AM3358

TLV320DAC3100: TLV320DAC3100IRHBR

Upendra Kumar
Prodigy 110 points
Part Number: TLV320DAC3100

Hi, 

     I'm Transmitting audio data over I2S protocols, By help of analyzer i have verified the audio data its working fine, but tlv320dac3100 producing noise.

please find my  tlv320dac3100 configuration..

i2cset -y -r 2 0x18 0x00 0x00
i2cset -y -r 2 0x18 0x01 0x01
i2cset -y -r 2 0x18 0x04 0x03
i2cset -y -r 2 0x18 0x06 0x08
i2cset -y -r 2 0x18 0x07 0x00

i2cset -y -r 2 0x18 0x05 0x91
i2cset -y -r 2 0x18 0x0B 0x88
i2cset -y -r 2 0x18 0x0C 0x82
i2cset -y -r 2 0x18 0x0D 0x00

i2cset -y -r 2 0x18 0x1B 0x00
i2cset -y -r 2 0x18 0x3C 0x0B
i2cset -y -r 2 0x18 0x00 0x08
i2cset -y -r 2 0x18 0x01 0x04
i2cset -y -r 2 0x18 0x00 0x00
i2cset -y -r 2 0x18 0x74 0x00

i2cset -y -r 2 0x18 0x00 0x01
i2cset -y -r 2 0x18 0x1F 0x04
i2cset -y -r 2 0x18 0x21 0x4E
i2cset -y -r 2 0x18 0x23 0x44
i2cset -y -r 2 0x18 0x28 0x06


i2cset -y -r 2 0x18 0x29 0x06
i2cset -y -r 2 0x18 0x2A 0x1C
i2cset -y -r 2 0x18 0x1F 0xC2
i2cset -y -r 2 0x18 0x20 0x86
i2cset -y -r 2 0x18 0x24 0x92
i2cset -y -r 2 0x18 0x25 0x92
i2cset -y -r 2 0x18 0x26 0x92

i2cset -y -r 2 0x18 0x00 0x00
i2cset -y -r 2 0x18 0x3F 0xD4
i2cset -y -r 2 0x18 0x41 0xD4
i2cset -y -r 2 0x18 0x42 0xD4
i2cset -y -r 2 0x18 0x40 0x00

Please help to resolve this problem.

  • 0
    TI__Guru* 84915 points

    Hi, Upendra,

    Welcome to E2E and thank you for your interest in our products!

    Could you provide details about the clock frequencies you are using (MCLK, BCLK, WCLK)? In addition, could you provide the TLV320DAC3100 portion schematic, please? Finally, do you have details about the output noise? Is it in the audible band? Do you have some captures testing a 1KHz sine wave?

    This information would be useful in order to have a better approach to this issue.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 110 points

    Hi Luis,

          Thank you for response of my query.

               I'm providing external Clock From CRO at 11.2896 MHz For MCLK or BCLK are 2Mhz, WCLK 31.291 KHz.0724.data.zip

  • 0 in reply to Upendra Kumar
    TI__Guru* 84915 points

    Hi, Upendra,

    Thank you for providing the clock settings you are using. It actually seems to be associated to this problem. WCLK should be equal to the sampling rate you are configuring. In this case, the PLL settings you are using result in a sampling rate of 44.1KHz.

    So, my recommendations are:

    1) Use clock settings accordingly to the PLL and clock dividers settings. This is WCLK = 44.1KHZ and BCLK = 2.8224 MHz.

    2) Or use different PLL settings that result in the WCLK frequency value you are using. I would suggest to change MDAC from 2 to 3:

    i2cset -y -r 2 0x18 0x0C 0x83

    This would result in an approached sampling rate of 29.4KHz. In order to be more precise, you may use the following PLL and dividers configuration:

    P = 1
    R = 1
    J = 7
    D = 4502
    NDAC = 3
    MDAC = 7
    DOSR = 128

    This results in the same frequency you are using.

    I hope this makes sense. Please let me know if you have additional questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 110 points

    Hi Luis,

           I need to verify the speaker. so therefore i connected the headphone to AIN 2 pin and then i played the audio song but it's not working..
     I have configured the register..
    i2cset 0x18 00 00 # change to Page 0
    i2cset 0x18 40 0C # mute DACs
    i2cset 0x18 26 0x1 # wait for DAC gain flag to be set  92(Enable Class-D output analog volume, set = -9 dB)
    i2cset 0x18 0B 02 # power down NDAC divider
    i2cset 0x18 47 80 # enable beep generator with left channel volume = 0dB, volume level could
    # be different as per requirement
    i2cset 0x18 0B 82 # power up NDAC divider, in this specific example NDAC = 2, but NDAC could
    # be different value as per overall setup
    i2cset 0x18 40 00 # un-mute DAC to resume playing audio
  • 0 in reply to Upendra Kumar
    Prodigy 110 points

    Hi Luis,

           I need to verify the speaker. so therefore i connected the headphone to AIN 2 pin and then i played the audio song now it's working,
    but how to increase volume, please share the register setting..
  • 0 in reply to Upendra Kumar
    TI__Guru* 84915 points

    Hi, Upendra,

    Regarding the output volume, the registers associated to the volume are listed below:

    Speaker attenuation block (0.5dB steps): Page 1 / Register 38
    Speaker gain block (6dB steps): Page 1 / Register 42
    Left headphone attenuation block (0.5dB steps): Page 1 / Register 36
    Left headphone gain block (1dB steps): Page 1 / Register 40
    Right headphone attenuation block (0.5dB steps): Page 1 / Register 37
    Right headphone gain block (1dB steps): Page 1 / Register 41

    Please consult the functional block diagram for details:

    https://www.ti.com/lit/ds/symlink/tlv320dac3100.pdf#page=2

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 110 points

    Hi Luis,

         As per our conversation the MCL clock should be at 11.2896 Mhz and SCK  2.8224 Mhz  and FS 44.1 khz but I can not able to  provide exact clock frequency,  I have configured MCL at 12Mhz , SCK 1.5 Mhz and FS 46.5 Khz. There are any possibility to change the configuration in TLV320DAC3100 as per my clock configuration. Let me know if any possibility.

    Please check the audio and clock frequency in attachment file.

    8561.Data.zip 

  • 0 in reply to Upendra Kumar
    TI__Guru* 84915 points

    Hi, Upendra,

    Yes, it is possible to change the configuration of the TLV320DAC3100 for these values. However, it is important to consider that there could be some sampling issues (probably on the LSB of the sampled data) since the clocks are not multiple between them.

    The suggested values are listed below:

    P = 1
    R = 1
    J = 6
    D = 9440
    NDAC = 7
    MDAC = 2
    DOSR = 128

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 110 points

    Hi, Luis,

              I have configured the TLV320DAC3100 as per our conversation but still getting noisy sound could you please explain, how you can decided J, D, NDAC, MDAC, DOSR Value.

    Suppose My Clock Setting are: MCK  12 MHz or SCK 1.5 MHz and FS 46.8 KHz.

             P = 1
             R = 1
             J = 6
            D = 9440
            NDAC = 7
            MDAC = 2
            DOSR = 128

  • 0 in reply to Upendra Kumar
    TI__Guru* 84915 points

    Hi, Upendra,

    The most important thing when selecting the clock dividers and PLL values is to respect the maximum TLV320DAC3100 clock frequencies and the PLL formulas listed in page 54 and 55 of the datasheet ( https://www.ti.com/lit/ds/symlink/tlv320dac3100.pdf#page=54 ).

    However, you may also use our calculator tool of the SLAC366A.

    This codec control tool is used to configure the TLV320AIC3100-U (and similar devices). These devices share a similar clock tree than the TLV320DAC3100, so the calculator tool can be used for this device too.

    Open the codec control software, go to File Menu and select the New EVM Simulation option. You will see many available devices for simulation purposes. Select the TLV320AIC3100EVM-U. You will see a block diagram open in the main window. Go to the Digital Audio Processing block and then go to Internal Clock Gen Module block in the new displayed diagram. You will have access to the Digital configuration.

    Please let me know if you have additional questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 110 points

    Hi Luis,

    Please find attached file having:

    1. tlv_i2c_configuration_script

    2. tlv_i2c_script_logs

    After running the configuration script, the read back data for 0x01 register of page 0 is mismatched. May you please tell its impact.

    3. Snapshots of CRO captured frequency data of I2S lines

    Now we are running I2S with MCK - 11.2896MHz, FS - 44.1KHz, SCK - 1.411MHz

    4. Schematic_TLV320DAC3100_Portion

              May you please verify our hardware schematic document.  

    5. Audio file and its hex-dump

    We have configured our micro controller (ATSAMD21J18A) with settings - Stereo, 16Bit and tested it by playing short(2 sec) wav file repeatedly. The listed file formats have been tried:

    44.1KHz / 16KHz, 16bit Stereo, PCM

    We are using xxd to create hex data of the wav file, with command : 

    xxd -i file.wav > file.h

    tlv_i2s.zip

  • 0 in reply to Upendra Kumar
    TI__Guru* 84915 points

    Hi, Upendra,

    Thank you for the information you have provided.

    Regarding your question about the Page 0 / Register 0x01, you should always read 0x00 on this bit since the value is automatically cleared after the software reset.

    Regarding the schematic, do you have captures of the outputs before and after the registers configuration? Do you see any Class-D activity when the registers are written? Could you try removing the output LC filter?

    In this line:

    # DOSR = 128, DOSR(9:8) = 0, DOSR(7:0) = 128
    i2cset -y -r 2 0x18 0x0D 0x8000 w

    It seems that the register 0x0D is written as 0x8000. Does this refer to 0x0D = 0x80 and 0x0E = 0x00 or vice versa? The correct writing should be 0x0D = 0x00 and 0x0E = 0x80.

    Could you verify that the data you are sending is 2's complement, signed data? I think the PCM data has some differences with the I2S mode.

    Best regards,
    Luis Fernando Rodríguez S.