This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hello,
Could you share a little more information about your register settings and/or processing blocks being used? These devices have a lot of configuration settings and it's hard to determine the expected operation without understanding how it's being configured.
Hi Collin,
Please find the alsamixer settings we made additionally for recording and playback:
1) PCM (LDAC_VOL, RDAC_VOL ) gain as maximum (0dB)
2) HP DAC (DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL ) gain as maximum (0dB)
3) LINE1R_2_RADC_CTRL & LINE1L_2_RADC_CTRL as differential.
Please find the steps we followed for recording:
i2cset -f -y 2 0x18 0x1a 0x80
i2cset -f -y 2 0x18 0x1d 0x80
i2cset -f -y 2 0x18 0x0c 0xa0
i2cset -f -y 2 0x18 0x6b 0xc0
i2cset -f -y 2 0x18 0x19 0x40
arecord -c 2 -d 10 -D hw:0,0 -r 8000 -f S16_LE test.wav
Hello Jilu,
Can you please share the following:
- I2C transactions
- Full register dump
- Schematic
- Scope shots of BCLK, WCLK DIN/DOUT
There are several reasons that may cause unwanted noise in the recording path including incorrect PLL configuration, grounding issues, incorrect device configuration and incorrect ASI bus configuration. Providing the above requested information will help narrow down some possible causes.
Regards,
Aaron
Hi Aaron,
Please find the attached required documents.Audio Issue_Required Docs.zip
Hello Jilu,
Thanks for providing the requested info. Another question I have is what is the MCLK frequency being provided to the device? Based on the PLL configuration I would expect it to be 2.048MHz.
It would also be good to see WCLK and BCLK on the same capture to make sure they are aligned correctly.
Regards,
Aaron
Hello Jilu,
I look at the register configuration again and see that you are using BCLK as the PLL input clock. Doing so will not generate the proper Fs with BCLK = 255kHz as shown above. The minimum PLL input clock frequency is 512kHz. Since the PLL is expecting an input clock frequency of 2.048MHz, can you please provide a BCLK of 2.048MHz and see if this noise issue goes away?
Regards,
Aaron