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TLV320AIC3104: Routing Audio Issues (Bypassing I2S processing)

Part Number: TLV320AIC3104

I am trying to just do a very basic input to output so that I can test my external hardware interfaces before we start any I2S handling, but I cannot seem to route the audio through the codec as I would think that I can.  Maybe I am not configuring all of the registers that I need to?

I am trying to basically directly connect MIC2L to the Right LOP/M Differential Output not applying any gain (0dB) through the chain.  I am trying to do this by connecting MIC2L to the Left PGA and then routing the PGA_L output to the Right LOP/M bypassing all digital processing entirely (no I2S interface connected yet).

I have solid 0.707Vrm SE 3kHz sine wave from my function generator connected to MIC2L through a simple AC coupling cap to block the DC bias from the codec.  I am measuring the signal (DC Referenced) after the capacitor and can see the codec adding the proper DC bias to operate from 0vp to 2Vp as I would expect.  I also am measuring the Right LOP/M output but I am not seeing anything at all out of the codec.

I am using a Linux machine to control the I2C configuration registers and believe I am setting all of the registers correctly, but perhaps I am missing some settings?

Here are the registers and settings I am applying:

i2cset -y 1 0x18 0x01 0x80   Self-clearing software reset
i2cset -y 1 0x18 0x00 0x00   Sets to use Page 0
i2cset -y 1 0x18 0x11 0x0F   Connects MIC2L to Left ADC PGA Mixer and 0dB gain
i2cset -y 1 0x18 0x0F 0x00   Set Left-ADC PGA to not Muted & gain of 0dB
i2cset -y 1 0x18 0x51 0x80   PGA_L Output Routed to Left LOP/M
i2cset -y 1 0x18 0x56 0x09   LEFT_LOP/M not muted, fully powered up

 

And here is the i2c dump after applying these settings:

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f 0123456789abcdef
00: 00 00 00 10 04 00 00 00 00 00 00 01 00 00 00 00 ...??......?....
10: 80 0f ff 78 78 78 78 78 78 06 00 fe 00 00 fe 00 ??.xxxxxx?.?..?.
20: 00 00 00 00 80 00 00 00 00 00 00 80 80 00 00 00 ....?......??...
30: 00 00 00 04 00 00 00 00 00 00 04 00 00 00 00 00 ...?......?.....
40: 00 04 00 00 00 00 00 00 04 00 00 00 00 00 00 00 .?......?.......
50: 00 80 00 00 00 00 0b 00 00 00 00 00 00 00 10 00 .?....?.......?.
60: 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 ......?.........
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 10 04 00 00 00 00 00 00 01 00 00 00 00 ...??......?....
90: 80 0f ff 78 78 78 78 78 78 06 00 fe 00 00 fe 00 ??.xxxxxx?.?..?.
a0: 00 00 00 00 80 00 00 00 00 00 00 80 80 00 00 00 ....?......??...
b0: 00 00 00 04 00 00 00 00 00 00 04 00 00 00 00 00 ...?......?.....
c0: 00 04 00 00 00 00 00 00 04 00 00 00 00 00 00 00 .?......?.......
d0: 00 80 00 00 00 00 0b 00 00 00 00 00 00 00 10 00 .?....?.......?.
e0: 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 ......?.........
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

Any help would be greatly appreciated. 

Thank you,

 




  • Hi Gregory,

    The following app note shows information and register scripts for using the bypass feature in the TLV320AIC3109 and the same concepts apply to the AIC3104.

    https://www.ti.com/lit/an/slaa915/slaa915.pdf

    Could you take a look and see if the configurations get things working?

  • I looked through the document and it looks like I am doing it correctly.  I am not sure why it is not working.  Perhaps the hardware is somehow affecting the output circuit?

    Now I am just trying to use the left channel MIC2L to LEFT LOP/M output using the PGA Bypass method.

    Below are the settings being applied, which should match to the 3109 app note document you provided.

    /* Self clearing Software Reset and set to Page 0 */
    i2cset -y 1 0x18 0x01 0x80 // Self-clearing software reset
    i2cset -y 1 0x18 0x00 0x00 // Sets to use Page 0

    /* Route MIC2L to Left PGA */
    i2cset -y 1 0x18 0x11 0x0F // Routes MIC2L to Left ADC PGA Mixer and sets 0dB gain

    /* Route PGA_L to LEFT_LOP/M */
    i2cset -y 1 0x18 0x0F 0x00 // Unmute Left-ADC PGA and set gain to 0dB
    i2cset -y 1 0x18 0x51 0x80 // PGA_L Output Routed to Left LOP/M and sets 0dB gain
    i2cset -y 1 0x18 0x56 0x09 // Unmute LEFT_LOP/M, set to fully powered up and output level set to 0dB


    After a dump of the registers I see that 0x56 (Register 86) shows LEFT_LOP/M Volume Control Status as 1 (Not all programmed gains to LEFT_LOP/M have been applied yet). Could this be an issue? If so, when and how would this 
    get set to a 0 indicating the gains have been programmed?


         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f 0123456789abcdef
    00: 00 00 00 10 04 00 00 00 00 00 00 01 00 00 00 00 ...??......?....
    10: 80 0f ff 78 78 78 78 78 78 06 00 fe 00 00 fe 00 ??.xxxxxx?.?..?.
    20: 00 00 00 00 a0 00 00 00 00 00 00 80 80 00 00 00 ....?......??...
    30: 00 00 00 04 00 00 00 00 00 00 04 00 00 00 00 00 ...?......?.....
    40: 00 04 00 00 00 00 00 00 04 00 00 00 00 00 00 00 .?......?.......
    50: 00 80 00 00 00 00 0b 00 00 00 00 00 00 00 10 00 .?....?.......?.
    60: 00 02 00 00 00 00 02 00 00 00 00 00 00 00 00 00 .?....?.........
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    80: 00 00 00 10 04 00 00 00 00 00 00 01 00 00 00 00 ...??......?....
    90: 80 0f ff 78 78 78 78 78 78 06 00 fe 00 00 fe 00 ??.xxxxxx?.?..?.
    a0: 00 00 00 00 a0 00 00 00 00 00 00 80 80 00 00 00 ....?......??...
    b0: 00 00 00 04 00 00 00 00 00 00 04 00 00 00 00 00 ...?......?.....
    c0: 00 04 00 00 00 00 00 00 04 00 00 00 00 00 00 00 .?......?.......
    d0: 00 80 00 00 00 00 0b 00 00 00 00 00 00 00 10 00 .?....?.......?.
    e0: 00 02 00 00 00 00 02 00 00 00 00 00 00 00 00 00 .?....?.........
    f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

     

    If the above looks correct, perhaps there is something wrong with the circuitry directly connected to the codec LEFT_LOP/M?  See below.  All output measurements were being measure from Test Point 15 (TP15).

    Thanks!

  • Hello Gregory,

    The initial configuration you provided seemed to be correct but went ahead and ran it on an EVM for a sanity check. I was able to get data on LEFT_LOP.  You can see this in the scope shot below. Channel 1 is the input and Channel 2 is probed at LEFT_LOP pin. There you can see the applied CM voltage. 

    i2cset -y 1 0x18 0x01 0x80   Self-clearing software reset
    i2cset -y 1 0x18 0x00 0x00   Sets to use Page 0
    i2cset -y 1 0x18 0x11 0x0F   Connects MIC2L to Left ADC PGA Mixer and 0dB gain
    i2cset -y 1 0x18 0x0F 0x00   Set Left-ADC PGA to not Muted & gain of 0dB
    i2cset -y 1 0x18 0x51 0x80   PGA_L Output Routed to Left LOP/M
    i2cset -y 1 0x18 0x56 0x09   LEFT_LOP/M not muted, fully powered up

    So you had the configuration correct at the beginning. Some questions moving forward:

    • Can you be sure the I2C communication is working correctly?
    • Can you probe directly at the LEFT_LOP pin of the device? If there is no clear pass through of the input signal, is there a visible CM voltage? seeing a CM voltage there 

    As for your question about the programmed gain, there is actually a data sheet error (Currently in the process of getting fixed) where it should read:

    D1 = 0 when "not all programmed gains to ___ have been applied yet".
    D1 = 1 when "all programmed gains to ___ have been applied".

    So I would not worry here. 

    Regards,

    Aaron

  • Hi Aaron,

       I was able to access the LEFT_LOP/M direct via the R141 and R142 on the top of my board.  However, I did not see any voltage or CM voltage present when DC or AC coupled on the scope. 

    We are using 2 of these codecs on our board and each of them has its own dedicated I2C interface to our controller.  I configured both codecs identically just to make sure I wasn't setting up the wrong codec.  We also have a GPIO we use to reset the codecs.  I am now sure that I am communicating to the codecs and configuring them correctly since when I pull the reset lines down the I2C dump shows all XX's.  When I disable the reset line the I2C dumps, pre configuring, shows the default register values.

    I am still confused why I am not seeing an output on either codec.

    Here is the main wiring of the codec.  Do you see any issues here?

  • Hello Gregory,

    The only worry I see from the schematic are the pull down resistors on the inputs. I see they are DNI so are they unpopulated on your board? Unused inputs should be connected to GND via 0.47uF capacitor. 

    Can you share some I2C transactions? I would like to take a look at them if possible. 

    Regards,

    Aaron

  • Hi Aaron, That is correct. All DNI are not populated. The only I2C transactions ai am doing are the i2cset commands and then the i2cdump command to verify each register has been correctly set to that value. I have done one by one verification at least to that level. Is there something more detailed that you are looking for? Thanks!
  • Hi Aaron,

       I did some snooping on the I2C within linux.  Does this help?

    Thanks!

  • Hi Gregory,

    Reading register writes is nice but I would like to visually see that the device is getting configured. As for some next moves, is it possible for you to remove R141 and R142 and then probe the device output? I would just like to isolate the Codec's outputs. 

    I am not sure what the RIGHT_LOP/M outputs are being used for but can you try and power on the driver by writing 0x0B to register 0x5D? You may also try one of the HPOUTs. HPROUT driver can be powered on by writing 0x0B to register 0x41. This is just to ensure we can visually see the device getting configured correctly. These outputs should show the default ~1.3V CM when powered on. 

    Regards,

    Aaron

  • Thanks for the help guys.  I was able to find our problem yesterday.  The settings were correct, but getting routed to the wrong codec.  We had an internal documentation error on a test point for our second codec.  The short story is that i2cset -y 1 XXXX XXXX commands were actually setting up codec 2 instead of codec 1 which I was interfacing with.  When I was injecting the signal to codec 2 it was actually on the wrong test point since we had a documentation error.  All works correctly now as expected now.  I do have another question about input voltage levels which I will start a new post on for best tracing.

    Thanks again!