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Original question:

PCM6240-Q1: I2C fall time not meet the spec

PCM6240-Q1: BCLK rise and fall time

user6199457
Prodigy 120 points
Part Number: PCM6240-Q1

In the datasheet I found BCLK time requirements in below two places.

1)What's the difference about the BCLK rise and fall time between Timing requirements(rise:10ns, fall:10ns) and Switching characteristics(rise:10ns, fall:8ns)??

2)In our application, PCM6240 is setup slave mode, and I tested waveform is about 10ns at PCM6240 BCLK pin.

Could you help to provide the TDM time sequence requirement about PCM6240 working at slave mode?

3)If BCLK rise and fall time is tested as I provide, and assuming the rise time and fall time requirement is 10ns, what problems will be happen?

  • 0
    TI__Mastermind 23050 points

    Hi,

    The difference in the specifications is in the first table these are the general specifications for the interface. In the second table, the spec is with BCLK as an output since the device is acting as a master, so the difference is whether the clocks are inputs or outputs.

    I don't see any problems in the waveform you have attached so you should be fine. The main purpose of these specs is to ensure a stable edge that can be clocked, if the waveform is too fast the edge may not be captured at the right time possibly leading to more jitter in your data. You should not have problems here but you could try to increase the series resistance on the line if it is a concern.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 120 points

    Hi,

    Your mean, in timing requirement table include master mode and slave mode? And in switching characteristics, is only master mode requirement?

    In my design, the series resistance is selected 33R. But in order to meet the maximum time rise and fall 10s, I must to decrease the resistance value or increase the drive ability of DSP(master device).

    According to what your said, the rise and fall time need to rule the minimum time not the maximum time in the spec. Am I right?

    And compared with TLV320AIC3109 spec which rise and fall time are fully separate, in PCM6240 spec may have a little confusing. Especially what is the criterion for judging the rise and fall time when PCM6240 is working in slave mode?

  • 0 in reply to user6199457
    TI__Mastermind 23050 points

    Hi,

    Yes, the timing requirements section of the specifications refer to specs that need to be met to guarantee proper operation of the interface, i.e. with pins operating as inputs and thus in slave mode. The switching characteristics section specifies how the device behaves when it controls these nodes and you see in the specs that they say master mode. 

    I apologize I misread your initial concern. Yes the specs give the maximum amount of time it should take for the signals to rise or fall, if you are operating faster than this it is okay. Since your rise time exceeds 10ns, you may want to decrease the series resistance or increase your DSP drive strength as you mentioned. 

    Best,

    Zak