Hello All,
We have purchased TLV320AIC3106. We are trying to connect the MIC 3R to HPLOUT our intention is Mic audio should be heard in speakers.
I have shared the configurations below for the path. Mic to HPLOUT audio is still not heard.
please confirm us if the configuration is correct since audio is not heard in speakers.
Codec configuration:
Codec is master, sampling frequency is 48000 Hz
Please reply at the earliest.
Regards,
Dilip
aic3106.c
aic3106codec.h
/* Page 0*/ WriteRegister(AIC3106_REG0_PAGESELECT, 0)) /* Write software reset */ WriteRegister(AIC3106_REG0_RESET, 0x80)) /* N(ADC/DAC) = 1*/ WriteRegister(AIC3106_REG0_CODEC_SAMPLE_RATE, 0x00)) /* PLL disabled, Q = 2*/ WriteRegister(AIC3106_REG0_PLL_A, REG_PLL_A_96KHZ)) /* Write CODEC data path */ WriteRegister(AIC3106_REG0_CODEC_DATAPATH, 0x0A)) /* read back the CODEC data path */ ReadRegister(AIC3106_REG0_CODEC_DATAPATH, &newValue)) WriteRegister(AIC3106_REG0_ADDNL_GPIO_CONTROL_B, 0x01)) // CODEC_CLKIN uses CLKDIV_OUT ReadRegister(AIC3106_REG0_ADDNL_GPIO_CONTROL_B, &newValue)) WriteRegister(AIC3106_REG0_CLOCK_GEN_CONTROL, 0x02)) // CLKDIV_IN/PLLCLK_IN uses MCLK, /2 ReadRegister(AIC3106_REG0_CLOCK_GEN_CONTROL, &newValue)) /* Audio Serial Data Interface A */ WriteRegister(AIC3106_REG0_SERIAL_DATA_INTFC_A, 0xF0))//BCLK,WCLK is output ReadRegister(AIC3106_REG0_SERIAL_DATA_INTFC_A, &newValue)) /* Audio Serial Data Interface Control Register B */ WriteRegister(AIC3106_REG0_SERIAL_DATA_INTFC_B, 0x00)) //IIS mode 16 bit word bit length,continuous transfer mode ReadRegister(AIC3106_REG0_SERIAL_DATA_INTFC_B, &newValue)) /* Audio Serial Data Interface Control Register C */ WriteRegister(AIC3106_REG0_SERIAL_DATA_INTFC_C, 0x08)) //IIS mode 16 bit word bit length,256 frame transfer mode ReadRegister(AIC3106_REG0_SERIAL_DATA_INTFC_C, &newValue)) /* MIC3R --> Left ADC * |_> Right ADC */ /* AIC3106_REG0_LEFT_ADC_PGA */ WriteRegister(AIC3106_REG0_LEFT_ADC_PGA, 0x00)) // PGA gain=0db /* AIC3106_REG0_RIGHT_ADC_PGA */ WriteRegister(AIC3106_REG0_RIGHT_ADC_PGA, 0x00)) // PGA gain=0db /* AIC3106_REG0_LINE1L_LEFT_ADC */ WriteRegister(AIC3106_REG0_LINE1L_LEFT_ADC, 0x7C)) //input 1 off, Left ADC powered up /*AIC3106_REG0_LINE1R_RIGHT_ADC*/ WriteRegister(AIC3106_REG0_LINE1R_RIGHT_ADC, 0x7C)) //input 1 off, Right ADC powered up /* MIC3LR_LEFT_ADC */ WriteRegister(AIC3106_REG0_MIC3LR_LEFT_ADC, 0xF0)) //MIC3L not connected and Mic3R is connected to Left ADC PGA /* MIC3LR_RIGHT_ADC */ WriteRegister(AIC3106_REG0_MIC3LR_RIGHT_ADC, 0xF0)) //MIC3L not connected and Mic3R is connected to Right ADC PGA /* MIC3R MIC BIAS setting */ WriteRegister(AIC3106_REG0_MICBIAS, 0x80)) //MICbias is powered down to 3.3 V,Digital MIC is enabled /* Mid Processing Block * AGC is powered down, */ WriteRegister(AIC3106_REG0_LEFT_AGC_CNTL_A, 0x00)) // Left AGC disabled WriteRegister(AIC3106_REG0_RIGHT_AGC_CNTL_A, 0x00)) //Right AGC disabled WriteRegister(AIC3106_REG0_DAC_POWER_OUTPUT_DRVR, 0xE0)) // l/r DACs on, HPLCOM single-ended WriteRegister(AIC3106_REG0_HI_POWER_OUTPUT_DRVR, 0x10)) // HPRCOM single-ended //#if 0 WriteRegister(AIC3106_REG0_LEFT_DAC_VOLUME, 0x00)) // gain=0db WriteRegister(AIC3106_REG0_RIGHT_DAC_VOLUME, 0x00)) // gain=0db WriteRegister(AIC3106_REG0_DAC_L1_TO_HPLOUT, 0x80)) // DAC_L1 is routed to HPLOUT WriteRegister(AIC3106_REG0_HPLOUT_OUTPUT_LEVEL, 0x09)) // HPLOUT on WriteRegister(AIC3106_REG0_HPLCOM_OUTPUT_LEVEL, 0x00)) // 0db
