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PCM1840EVM: No data output at 4ch 96KHz TDM master mode

Mochi
Genius 3865 points
Part Number: PCM1840EVM
Other Parts Discussed in Thread: PCM1840, TLV320ADC6140, TLV320ADC3140

Hello,

Our customer has got PCM1840EVM to confirm 4ch TDM master mode function.

There is strange behavior, at 44.1KHz TDM master mode is worked fine, all clocks and data were outputted at MSZ=H, FMT1=L, FMT0=L,MD0=L, MD1=MCLK 11.2896MHz

Then change MCLK to 24.576MHz as 256fs of 96KHz TDM master mode, we got right timing FSYNC/BCLK output clocks as attached capture image, but SDOUT is always 0.

Fs 88.2KHz is same situation.

 

Should we set decimation filter order by manually to PCM1840?

Or some kind of setting is required on the EVM?

 

Our customer need to release PCB layout quickly to replace a ADC from AKM.

Regards,

Mochizuki

  • 0
    TI__Mastermind 23050 points

    Hi Mochi,

    Unfortunately this is a limitation of the PCM1840. It is only able to operate up to 48kHz as the bus master because operating at higher rates would require use of the PLL, which cannot be programmed given the limited number of HW control pins. If they need 96kHz operation as the bus master then I would urge them to look at TLV320ADC6140. This is the high performance software controlled version in this family and offers much more flexibility.

    There is an app note in the TLV320ADCx140 product folders that discusses operating the device in master mode and shows the limitations to channel count at higher sampling rates.

    Note that PCM1840 can still operate up to 192kHz as long as the clocks are provided from a master IC!

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Genius 3865 points

    Hi Zak,

     

    It is kind of big surprise for the customer because PCM1840 datasheet does not describe this fundamental function limitation.

    I hope to see revised datasheet very soon.

     

    Their system is 20ch digital audio, an original plan was that 4pcs of PCM1840 are mounted and 3 of them in Slave mode with one master mode PCM1840 to provide 96KHz BCLK and LRCK.

    The solution will be add master clock generator IC or replace one of PCM1840 to TLV320ADC6140 with I2C register control.

    It seems large PCB design and SW modification to replace AKM ADC by next month.

    Is there any way to find HW controlled 96KHz TDM master mode ADC in your lineup?

     

    Regards,

    Mochizuki

  • 0 in reply to Mochi
    TI__Mastermind 23050 points

    Hey Mochizuki,

    I am sorry for the confusion here and I agree this is something we will want to fix in the next datasheet revision.

    I am not sure if customer is aware though but it is also not possible to operate multiple PCM1840 devices on the same TDM bus because there is no way to offset the data and the device does not have daisy chain TDM capability. Were they using multiple data lines for this?

    Unfortunately we do not have any HW controlled ADCs that will support the number of channels required by the customer so the only option is to use a SW controlled device if they need all the data on a 20 channel TDM bus.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Genius 3865 points

    Hi Zak,

    Thank you for your support.

     

    Our customer agreed to move TLV320ADC3140 and we rent EVM to verify TDM master mode interface.

     

    Regards,

    Mochizuki