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PCM1802: BCLK/LRCLK input sequence

Part Number: PCM1802

Hi,

Could you tell us when should we input BCLK and LRCLK?

My customer says that they have heard from TIer five years ago that BCLK and LRCLK should be inputted after 1024 System clocks and 4480/fs as below.

However, there is no such sequence information on the datasheet, so we can not see if this information is correct.

The reason they heard the information is PCM1802 had a problem that data became abnormal depending on the power supply start timing, and the cause was power-on reset timing.

The above sequence seemed to be shown as the workaround.

Could you check if this information is correct?

Best Regards,

Kuramochi

  • Hello Kuramochi,

    To be honest, this is not a requirement we've heard before, or one we could find reference to in the E2E or our internal support archives.  Here is a post from 5 years ago which suggests the datasheet sequence is correct.  https://e2e.ti.com/support/audio/f/6/t/432434

    These products have been around longer than I've been supporting them so it's very possible the customer was told this, or tried this successfully in the past. Since we haven't heard of this recently our best guidance is to follow the datasheet recommended instructions.  Most systems output the SCLK, BCLK, and LRCLK as pairs and when one is enabled, all are enabled so we would expect the device to respond well when used that way. 

    If the customer is very interested in making sure there isn't any incorrect or invalid data clocked out, then if BCLK and LRCLK are held LOW until the point noted in your diagram then DOUT would not put out any possibly unwanted data and this would be very safe.