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PCM1802: OSR

Part Number: PCM1802

Hi,

It is written the following on the datasheet.

"The ×128 mode is available for fS < 50 kHz, and must be used carefully as the duty cycle of the 384 fS system clock affects performance."

Is it only 384fs we must be used carefully?

I would like to know about the case of 256 fs and 512.

Best Regards,

Kuramochi

  • Hi Kuramochi,

    I believe this statement is made because operating the modulator at a higher clock rate means that the adc conversion may be more sensitive to phase noise/ jitter on the system clock. System clocks greater than 256*fs actually get internally divided down to 256*fs anyways so this helps cut down the jitter a bit too. It is always best to provide a high quality system clock and you certainly want to avoid one with significant duty cycle variations.

    Best,

    Zak 

  • Hi Zak-san,

    Thank you for your reply.

    Is the internal 256*fs clock generated from the system clock?

    If yes, the falling edge of the system clock may be used to generate the internal 256*fs as below.

    I assume that this is the reason that " the duty cycle of the 384 fS system clock affects performance.".

    What do you think?

    Best Regards,

    Kuramochi

  • Hi Kuramochi-san,

    Yes the internal 256*fs clock is generated from SCKI for the 384*fs, 512*fs, and 768*fs input cases. I'm not sure exactly how the 1.5 internal divider for this is designed, but I think this is a fair assumption given the duty cycle concern that the falling edge is used by the divider.

    Best,

    Zak