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PCM1690-Q1: AMUTE and OPEDA register

Part Number: PCM1690-Q1

Hello Team,

I have question as below. Can you please support?

Q. For AMUTE[3:0], what is the asynchronous detect?

Q. For AMUTE[3:0], Does the DAC disable command means OPEDA=1?

Q. For OPEDA[3:0], Can we program SRDA during the OPEDA=0000(Normal operation)? Or should we set the OPEDA=1111(disable) firstly then program each setting?

Thanks,

Yuta Kurimoto

  • Hi Kurimoto-san,

    1. Asynchronous detect is described in the section "SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM"

    2. Yes, in this case, it would be OPEDA=1.

    3. You can configure the SRDA during normal operation, but I recommend you mute the output or ensure that DIN is zero.  The change should no be audible, but I think it would be prudent to ensure the output is idle as this register also store the FMTDA field.

    Thanks,

    Paul

  • Hello Paul,

    Thanks for your answer. 

    Q. In case AMUTE[3:0]=0000, when the each event(SCKI lost, asynchronous detect, ZERO1 and ZERO2 detect, DAC disable command) is occurred, what happen of the output voltage? Keep the output voltage level? Settle to VCOM level? impossible to predict what happen?

    Q. For the previous answer.3 about SRDA programming during normal operation. What are you concerned about? Pop noise? 

    In the customer's case, when they program the PCM1690-Q1, they always mute the power amp. In that case, is there any problem?

    Q. For the REVDA register, is there additional output delay time when they set inverted output compared with normal output? If yes, how much is the delay?

    Q. For the table.17 in the datasheet, it shows the attenuation level is -45.9dB when ATDAx[7:0]=10011100. Is it not 49.5dB but 45.9dB?

    Thanks,

    Yuta Kurimoto

  • Hello Paul,

    Sorry for asking again. Is it possible to answer the previous questions?

    In addition the question, I'd like to ask one more question.

    Q. Regarding with ZERO[8:1] read-only register, If we perform write access for these register, Is there no effect?

    Thanks,

  • Hi Kurimoto-san,

    For the previous answer.3 about SRDA programming during normal operation. What are you concerned about? Pop noise? "

    1. A. In the case where either SCLK is lost or an asynchronous clock is detected and analog mute is disabled, I would expect that the output would be in the "undefined" state until the clocks unsynchronized.  That usually means that the output is static on the last combination of current segments in the DSM, but when the device recovers, there could be a fast audible transient when the device resynchronizes.  I do not recommend disabling AMUTE for lost SCLK or asynchronous detects.

    1. B. If DIN = 0 and the AMUTE is disabled, nothing will happen.  The device will just continue to modulate the output at zero-scale (VCC/2).  It is not a problem.

    1. C. If the DAC is disabled but not allowed to enter analog mute, then I expect it would continue to operate as though DIN =0.  It would not be a problem, but the device would consume more current than necessary.

    2." For the previous answer.3 about SRDA programming during normal operation. What are you concerned about? Pop noise? "

    My concern would be that there is some kind of audible glitch, but I have not tested this in the lab.  

    "In the customer's case, when they program the PCM1690-Q1, they always mute the power amp. In that case, is there any problem?"

    That is a very good solution.  Having an external mute will nullify any pop concerns.

    3. "For the REVDA register, is there additional output delay time when they set inverted output compared with normal output? If yes, how much is the delay?"

    I would expect the output would invert immediately.  I recommend that the DIN = 0 or the device is muted, as the sudden inversion of the data might look like a very fast transient on the output.  

    4. "Q. For the table.17 in the datasheet, it shows the attenuation level is -45.9dB when ATDAx[7:0]=10011100. Is it not 49.5dB but 45.9dB?"

    That is a good catch! That is a typo, and the device would be at 49.5dB.

    5. "Regarding with ZERO[8:1] read-only register, If we perform write access for these register, Is there no effect?"

    I would not have any impact on the device.

    Thanks,

    Paul