Hi all,
My customer uses TLV320AIC3204 in their audio codec application with 12MHz MCLK input and need 48KHz WCLK to backend intel chip. We use different PLL setting to generate 48K and get different sound resunt (1KHz with different ... harmonic?). Is there any suggestion about PLL setting (P/R/J/D/dividers...) for our reference? Andy why different PLL setting (with same WCLK result) cause different sound heard?
Best regards,
Gary Teng