Part Number: TLV320ADC3140
On the datasheet of TLV320ADC3140 following section described operation at sleep to active mode.
It recommended to apply FSYNC and BCLK after writing P0_R2.
However our customer's DSP designed to keep output BCK.
Is there any concern to input BCK during sleep mode?
188.8.131.52 Detailed Design Procedure
5. Transition from sleep mode to active mode (again) as required for the recording operation:
a. Wake up the device by writing to P0_R2 to disable sleep mode
b. Wait for at least 1 ms to allow the device to complete the internal wake-up sequence
c. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
d. The device recording data are now sent to the host processor via the TDM audio serial data bus
There is no issue continuing to apply BCLK while the device is in sleep mode. The device buffer for BCLK will draw a very small current from IOVDD on the order of a few uA but this will not cause any problems.
Zak Kaye Precision Data Converter Applications
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In reply to Zak Kaye:
Thank you very much for your quick support.
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