• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 29 subscribers
  • Views 232 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

PCM1802: Question about Audio Data Interface Timing

PCM1802: Rise and fall time question

K.Shidara
Expert 3225 points
Part Number: PCM1802

Hi Zak-san

Would you advise additional 4 customer questions for below link of E2E answer at the bottom of this mail?

1. Rise and fall times are measured from 10% to 90% of IN to OUT signal swing.

Please tell me the meaning of this sentence after from. It can be taken to mean

"the time difference from the 10% level of the input signal to 90% of the output signal",

but it seems inappropriate as a definition of rise / fall time.

Is the measured value of rise / fall time of a single signal specified by the transition time of 10↔90%?

2. The rule that Rise / fall time of all signals <10ns is also described in Master mode on p20 / 34,

but in Master mode, all I2S related signals are output. Does this mean that the total I2S output of

PCM1802 satisfies @ 20pF load with a transition time of 10ns or less of 10↔90%?

3. About tr / tf 10ns max.

Applicable to LRCK and BCK When fs = 48kHz, LRCK t = 20.83us (20833ns), BCK t = 325ns,

which means that the signal has a very long period. Considering this, it looks like a very strict

condition, but is it necessary to meet 10ns max even under this condition?

* For example, This is at 192kHz case and at 48kHz there is some room for relaxation, etc?

4. What kind of problem can be considered if the 10ns spec cannot be met?

Thanks

Best regards,

Shidara

  • 0
    TI__Expert 3225 points

    Hi Zak-san

    Regarding above questions, is any update?

    Especially #1 question, This rise/fall time includes IC internal propagation delay.

    Is my understand correct?  

    Thanks

    Best regards,

    Shidara

  • 0 in reply to K.Shidara
    TI__Mastermind 23050 points

    Hi Shidara-san,

    The rise and fall time specify the transition time for either an input or an output signal to swing from 10% to 90% of the maximum value (or 90% to 10% in the case of fall time).

    Your interpretation of question 2 is correct. Rise and fall time specs in master mode describe how quickly the output signals will transition.

    The max rise and fall time should always be considered 10ns across sample rate. This is because the clock edges are important for keeping the system synchronized and excessively long rise or fall times can result in increased jitter, which may degrade the performance of the device.

    Best,

    Zak