PCM1802: FSYNC timing requirement

Ryo Akashi

Expert 8940 points

Part Number: PCM1802

Hello experts,

I have question about FSYNC.

If we use slave mode 24-bit, MSB-First, Left-Justfied, FORMAT 0, FSYNC is always High as Figure 23 mentioned.

But from Figure 24, FSYNC has the timing requirement for BCK.

I'm little bit confused to understand how to use FSYNC. How do we consider FSYNC signal?

I would appreciate if you would give me reply.

Thanks and best regards,

Ryo Akashi

over 3 years ago

0 Zak Kaye over 3 years ago

TI__Mastermind 23050 points

Hi Akashi-san,

It is fine to just keep FSYNC tied high. This device uses an abnormal interface to let you gate the BCK with the FSYNC, the timing is only relevant if this feature is used. I would recommend just tying FSYNC high though.

0 Ryo Akashi over 3 years ago in reply to Zak Kaye

TI__Expert 8940 points

Hello Zak-san,

Thank you for your reply.

I understand FSYNC tying High is fine.

You mean BCK timing is required for Interface Mode (in datasheet P21 7.4.5). Is my understanding correct?

Thanks and best regards,

Ryo Akashi

0 Zak Kaye over 3 years ago in reply to Ryo Akashi

TI__Mastermind 23050 points

Hi Ryo,

FSYNC is part of the interface and it you choose to toggle this signal in slave mode the setup time between FSYNC and the BCK rising edge should be taken into account as given in table 7, but this can be ignored if FSYNC is just tied high.

Best,

Zak

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PCM1802: FSYNC timing requirement