TLV320ADC3101: ADC3101 configuration for Master mode
Part Number: TLV320ADC3101
we are using the ADC3101 for data acquisition, we use it as the slave mode , and the timing is from the external MCU timing which is 32MHz, if we want to get
a sampling frequency of 22.05KHz fs, could you give me a setting demo about the register?
Nice to connect with you again. The team is tied up with a few other activities today and I wanted to jump in and quickly ask that you try entering the desired parameters into the Audio CODEC/ADC PLL calculator tool (link below) and use them to see if it's working properly. It's likely a slightly off divider setting.
The tool will also confirm that the configuration you're looking for is supported. Let us know how it goes and we'll keep supporting you.
Regards,Collin WellsPrecision ADC Applications
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In reply to Collin Wells:
we use the BCLK as the input of ADC, BCLK from the MCU is 5MHz. but still the result not work, is there anything else should we take care of?
In reply to wxyxiangyang:
the register setting is as below (red text), the BCLK from the MCU we measured is 5Mhz.
looking forward to the reply, thanks.
If your BCLK is 5MHz, you're not going to be able to run the device at a standard audio rate because your BCLK needs to be a multiple of your sample rate. You can use a non-audio MCLK to generate audio rate clocks using the PLL or run the device at non-audio rates, but if you are trying to run BCLK at a rate unrelated to WCLK this will not work.
Zak Kaye Precision Data Converter Applications
In reply to Zak Kaye:
Slave mode means you are supplying all of the clocks to the device and it just outputs the data, master mode means you provide it with a master clock and it generates the BCLK and LRCK based on how you program the dividers.
In either case it is necessary to program the PLL, dividers, and filter based on how you intend to use the part. All of our specifications and filter characterization is done with an AOSR of 32, 64, or 128, but as long as you abide by the restrictions given in section 11.2 and you AOSR is an integer multiple of the decimation factor then this should be fine.
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