PCM1840: Problems with lock of TDM4 data stream / PLL

Prodigy 40 points

Replies: 14

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Part Number: PCM1840

Hello,

We have implemented the PCM1840 ADC in several new and reworked designs. In only one case we are having heavy problems to get the converter running stable.

The problem we have:

After switching on the device and booting the DSP, there is either a "broken looking" data stream or just a zero out of the ADCs. All clocks are running and looking fine.

Now if I just "short" the LRCLK to ground, to skip it out for a moment and then release it, the converter starts working normal. Also if the converter is running normal and I set it to PDN, sometimes it comes up again and sometimes not. So my guess is, it might have something to do with the PLL of the converter?!

Both of the converter are acting similar and we even already replaced the parts with new ones.

The configuration:

2xPCM1840 running in TDM4 left-justified mode as slave hooked up to a ADAU1452 - one data line per converter to the DSP and a common BCLK and LRCLK from the DSP to the converters.

BCLK is running at 6.144MHz pos. Edge

LRCLK is running at 48kHz pos. Egde (right now we are running pulse mode, but also tried 50/50)

FMT1, FMT0, MSZ, MD0 are set to low

MD1 is switchable for DRE application.

The local layout and the power supply of the ADCs is similar to our running implementations of the device, if there are some critical points in layout and power, I can point out more details on this.

Did someone have a similar problem to this or an idea how to proceed the debugging?

Thanks for your help,

Florian

14 Replies

  • Hi Florian,

    Welcome to our e2e forum!  I'm sorry to hear that you are having issues with the PCM1840!  From the description above, it sounds like you are doing everything right.  My initial thought was that you might have an issue with the clock - over/under shoot, reflections, ringing, etc.  Do things happen to work better when you are probing the BCLK and/or FSYNC?  If you could pass over your layout, we'd be happy to take a look.

     

    Regards,

    Tom

  • In reply to Tom Hendrick:

     Hi Tom,

    I am the colegue of Florian and here you find a screenshot of the layout showing the section with the two PCM1840 and the ADAU1452.
    We are using a 6-layer pcb and all high-speed data lines are located in an inner layer (here the "green" layer). For better visuality the screenshot does not show the filled areas which are connected to ground.

    As Florian already mentioned this is the only project where we are facing such problems. Other devices with similar design/configuration did work properly right from the beginning.


    Regards,
    Robin 

  • In reply to Robin Krichel:

    Hi Robin!

    Thanks for the screen capture!  Was there a second screen shot that you meant to attach?  If so, it did not come through.  From the layout side, everthing seems correct as well - I don't immediately see any issues.  The two devices seem to follow the same basic pattern and I see that AVSS ties back to AGND @ C120 on IC1.  Is that a solid ground plane on the yellow layer or are all the grounds stiched together somehow?

    Funny thing - I can see the TSH, I used to add my initials to boards in a similar way TEH blends together nicely...

     

    Regards,

    Tom

  • In reply to Tom Hendrick:

    Hi Tom,

    no - there was no second screenshot. The yellow layer is a solid ground plane and we are using the fills of other layers as additional ground. All are properly connected by "tons" of vias.

    Regards,
    Robin

  • In reply to Tom Hendrick:

    Hi Tom,

    no - there was no second screenshot. The yellow layer is a solid ground plane and we are using the fills of other layers as additional ground. All are properly connected by "tons" of vias.
    I have added a more detailed scrrenshot of the ground connection of the PCM1840.

    Regards,
    Robin

  • In reply to Robin Krichel:

    Hi Robin,

    Thanks for confirming the layout.  Can you send over screen shots of the clock and data?

     

    Regards,

    Tom

  • In reply to Tom Hendrick:

    Hi Tom,

    unfortunately I do not have any screenshots of the clock signals available at the moment, but of course we already paid attention to this.
    Actually the wave forms of FYSNC and bit clock were almost perfect with sharp slope and negligible overshoot.
    So we are convinced that the clocks will not cause the problem.

    Regards,
    Robin

  • In reply to Robin Krichel:

    Hi Robin,

    Actually I was hoping you could provide a screen shot of the 'broken data', along with the BCLK for reference.

     

    Regards,

    Tom

  • In reply to Tom Hendrick:

    Hi Tom,

    thanks for your help so far!

    I made some screen shots of the clock- and data lines.

    This one shows a close up of the rising edge of LR&BCLK in "fail mode" purple is DATA OUT from the ADC:

    This is the same after "shorting the clock" running normal:

    This is 1FS of the fail state, again purple = DATA OUT:

    Same for running normal:

    Here a close up of LR/BCK

    Hope this helps!

    Thanks,

    Florian

  • In reply to FBalk:

    Hi Florian!

    Thank you for the screen shots!  Just to be sure that I understand correctly, in 'fail' mode, it looks like the SDOUT is stuck - repeating a pattern that is not valid data.  Is that right, like the "1FS of the fail state" above - that output pattern continuously repeats? 

     

    Regards,

    Tom