• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 32 subscribers
  • Views 1648 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TAS6424-Q1: FAULT/WARN PIN reporting datasheet error

Alexander Pisl
Prodigy 30 points

Part Number: TAS6424-Q1

Hi TI,

I am using the TAS6424-Q1 in a automotive amplifier application.

Developing the C code for the ATTiny managing the TAS, I noticed behaviour that was contradictory to the expected behaviour stated by the datasheet, concerning the /FAUL and /WARN PIN reporting. I also found a obvious error in the datasheet, which I will adress first becaus it proofs that this section of the datasheet has not been reviewed prooperly prior to release and therfore it is not deniable that my other found errors are legitimate errors as well and not only user mistakes.

I am refering to the current

dataheet TAS6424-Q1 SLOS870B –SEPTEMBER 2016–REVISED OCTOBER 2017 from www.ti.com/.../tas6424-q1.pdf

  1.  Page 45: 0 should be 1 Typo of Register 0x21 bit 4 Value (the mentioned obvious mistake, again this is just the opener so you hear me out on the next ones which really are importatn to me). See the picture below to find the mistake.


  2. Also on the page shown above the Reg 0x21 Bit 7 CLEAR FAULT which is used to reset the latching WARN Pin after Warnings are reporte could use more explaination. It seems to not only reset the WARN Pin, and the warnings register 0x13 but also the FAUT Pin and faults register 0x12. This should be mentioned because its took me a while to find out the hard way. It does not latch back that bit after writing to it, so do I need to write 0 to it after writing 1 to it in order to function properly? (until now i only write 1 to it every time I want it to reset, but I would like to

  3. Page 42: Register 0x14 FAULT/WARN Pin reporting masking. The OTSD reoprting to FAULT is actually the other way arround as described. When I initialize it 0xFF the Faultpin is not asserted at OTSD (also reg 0x21 bit 4 is set to 0 so it should report), when I set reg 0x14 to 0x00 the Fault is reported to the Fault pin. This is a behaviour that I observed and verified in testing mit my TAS in my amplifier and a Clima chamber with heavy output power, driving the TAS to OTSD. I also want to use the OTW but since previously it did not report to WARN Pin I just read reg 0x13 instead. (again needing to CLEAR FAULT with reg 0x21 Bit 7 everytime I have read it and changed OTW Control from Reg 0x01 bits 6-5). In my setup I can not test the behaviour of the other masking bits reporting to FAULT/WARN Pins but I assume they also behave inverse to the description in the datasheet.

  4. Also the TAS is not in "revocer from fault" by default other then described in 9.8.3.5 (last sentence) but in "report OTSD to FAULT PIN and do not do auto recover via reg 0x21 Bit 4  (but it does not report to FAULT due to the wrong value of reg 0x15 Bit 6 when initialize according to datasheet. 


Please, tell me the actual Reg 0x14 setting so everything except Clip detect is reported to FAULT/WARN Pins and while you are at it fix the datasheet. Also some more description on the behaviour of the REgister would be nice to find in a corrected datasheet version. This particular datasheet has the information thin spread and leaves a lot or room for specualtion of how the TAS actually needs to be configured.

Thank you very much for your effort in advance, also in case I should be the one mistake in some points I beg your pardon.