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PCM5102A: Question regarding clock halt

Kazuki Kuramochi
Expert 8350 points
Part Number: PCM5102A

Hello Expert,

I'd like to know about detailed behavior of PCM5102A regarding I2S clock halting.

First, they want to know how long does PCM5102A take time for finishing output ramp up.
We plan to unmute by XSMT pin 4ms after I2S signal is started to supply.
I think it take 4ms + 104samples to finish ramping up and output expected signal.
Is this understanding correct?

Second, I'd like to know about the pop noise concern under First question's situation.
I checked several thread on E2E which explained there is possibility to cause pop noise by releasing analog mute.
Then, I'd like to know about there is possibility to happen pop noise under first question's situation.
Would you tell me about whether there is possibility to happen pop noise under first situation?

Last, I'd like to know about the concern when happened I2S clock halt.
Is there any concern when I2S's MCLK/BCLK/LRCK is halted simultaneously?

I'm looking forward to hearing back from you.


Best regards,
Kazuki Kuramochi

  • 0
    TI__Guru 52683 points

    Hi Kuramochi-san,

    1. Your understanding is correct.  You could expect the ramp to complete in 104samples.

    2. The risk of pop noise occurs when the device enters or exits analog mute.  Analog mute will occur when one of the three conditions occur:

    a. The DIN signal is zero for 1024 samples. 

    b. There is a sustain synchronization error.  This will occur if the clocks stop.  The device will first ramp to full mute, and then few moments later the device will enter analog mute.  

    c. Asserting XSMT will cause the output to ramp to full mute, then a few moments later it will enter analog mute.

    Generally this pop noise is not audible, and can only be found in systems that have high external gain.

    Thanks,

    Paul