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TLV320ADC3101: Recording audio using only BCLK

Part Number: TLV320ADC3101


I'm recording audio using TLV320ADC and ESP32. The recorded audio is fine noise-wise, however it looks as if the signal is discretized at 8 times lower rate - each sample in the i2s data is repeated 8 times.

I'm targeting 2channel 16bit audio at 22050Hz; I've set up I2S connection with BCLK, WCLK and DATA connected(No MCLK);

I2S config:

static const i2s_config_t i2s_config = {
.mode = (i2s_mode_t)(I2S_MODE_MASTER | I2S_MODE_RX),
.sample_rate = SAMPLE_RATE,
.bits_per_sample = I2S_BITS_PER_SAMPLE_16BIT,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S_MSB,
.intr_alloc_flags = 0, // default interrupt priority
.dma_buf_count = 32,
.dma_buf_len = 1024,
.use_apll = true,
.tx_desc_auto_clear = false,
.fixed_mclk = 0

And TLV registry setup:


  i2c_write_reg_byte(1, 0x01); // reset
  vTaskDelay(20 / portTICK_PERIOD_MS); // give it 20ms

  i2c_write_reg_byte(4, 0x05); // Clocl-gen multiiplexing - Use BCLK clock coming from ESP via I2S
  i2c_write_reg_byte(5, 0x11); // Disable PLL

  i2c_write_reg_byte(18, 0x81); // NADC = 1, divider powered on
  i2c_write_reg_byte(19, 0x82); // MADC = 2, divider powered on

  i2c_write_reg_byte(27, 0x00); // mode is i2s, wordlength is 16, slave mode (default)

  i2c_write_reg_byte(61, 0x01); // Use processing block 1


  i2c_write_reg_byte(52, 0xfc); // Left ADC Input selection for Left PGA = IN1L(P) as Single-Ended
  i2c_write_reg_byte(55, 0xfc); // Right ADC Input selection for Right PGA = IN1R(M) as Single-Ended

  i2c_write_reg_byte(59, 0x00); // Left Analog PGA Seeting = 0dB
  i2c_write_reg_byte(60, 0x00); // Right Analog PGA Seeting = 0dB


  i2c_write_reg_byte(81, 0xC2); // Power-up Left ADC and Right ADC
  i2c_write_reg_byte(82, 0x00); // UNMUTE

I tried enabling tlv's PLL using: P: 1 R: 8 K: 16 NADC: 8 MADC: 4 AOSR:128 but it didn't yeild any useful results.

Any help getting the TLV to record with better quality is welcome.

  • Hi George,

    Have you reviewed your current PLL settings against our PLL calculator tool?  Perhaps there are some clocking optimizations. Would you confirm your BCLK frequency?


  • Thanks for the spreadsheet!

    My BCLK is 22050(samples) * 2(stereo) * 16(bit) = 0.7056MHz and I use it as both PLL_CLKIN and CODEC_CLKIN

    Following the datasheet guidelines I chose PLL setting: P: 1 R: 8 K: 16 NADC: 8 MADC: 4 AOSR:128

    The spreadsheet confirms those settings fit the known requirements. However I record mostly zeroed samples.

  • I've been tinkering with my setup. I added a MCLK connection from ESP32 to TLV with a clock of 5.6448MHz (8 times my BCLK).
    Using P:1; R:1 J:16; NADC:1; MADC:2; AOSR:128; I get a noiseless good quality recording(best one so far);
    There are a few things that I cannot make sense of:

    1. I was expecting ADC_fs should be 705khz but when the adc works correctly it is actually when it's value is 352.8KHz; Is ADC_fs per channel? That would make sense as 22050 * 16(bit) = 352.8KHZ
    2. If I use NADC:2 MADC:1 instead ( nadc 1 madc 2) recording stops working correctly; I was expecting that there won't be any difference and I haven't found any explanation in the datasheet

    After getting it to work with MCLK I tried again with BCLK only.
    The best result was using: P:1; R:8 J:16; NADC:1; MADC:2; AOSR:128; However it behaves just like the my initial non-PLL version did - samples are repeated 8 times each;

    I feel I'm missing some dependency knowledge about choosing the right settings.

    Any insight would be helpful

  • Any suggestions how to setup recording without the MCLK signal?

  • I still haven't been able to get any satisfactory result only using BCLK.
    Any suggestion what might be wrong with my implementation?

  • Hi Georgi,

    Thank you for your patience here. I've been looking into your issue and there are a few important things I'd like to highlight:

    1) The maximum sample rate supported by the device is only 96kHz, so configurations at 352.8kHz, especially with a source clock that is only 705.6kHz, could yield unexpected results since we don't test or ensure operation at this rate.

    2) The maximum ADC_MOD_CLK is 6.5MHz, which supports the common multiple of 6.144MHz needed to support 2 channels of 32-bit data at 96kHz. The way you show it above sets this considerably above its limit, so there again may be unexpected behavior. 

    3) Your initial script showed the PLL as disabled, but if you want to run the device from BCLK it will be necessary to use the PLL. Can you confirm that your initial 22.05kHz case was being tested with the PLL enabled?

    4) A sample rate of 22.05kHz is going to require you to use decimation filter A, so if you are using processing block 1 this should be suitable/

    5) Each processing block has a particular instruction count associated with it and is shown in table 6. The PLL calculator doesn't include this selection but there is an additional restriction shown in the clocking diagram (figure 28) where MADC x AOSR >= instruction count. In your example above this is the reason that NADC = 1 and MADC = 2 works but the reverse does not, because the instruction count for PRB1 is 188 and your AOSR is 128.

    6) Also just to confirm the ADC/DAC sampling rate is your LRCK frequency so you want this to match your intended sample rate rather than doubling it for 2 channels.

    I hope this helps!



  • Zak thanks for the hints!

    Yes, I'm enabling PLL

    They are quite logical and exactly are exactly how I expected the tlv to work. It seems to me that the ADC works at 16 times lower freq than I set it up so I'll try to measure the pll or other clocks from the tlv and then post my findings and progress.