TLV320ADC3101: Problems with Re-Sync feature

Part Number: TLV320ADC3101


 We have a problem with re-sync functionality. Here are some more details about our settings.

We use the "left justified mode" with 16 bits. BCLK and WCLK are provided by an external µC, codec acts as a slave. BCLK source is 8 MHz and is brought to 10.24 MHz by codec PLL. By 128 oversampling we then reach the ADC_FS of 8 kHz (= WCLK).

In our case, that means that the jitter of the rising WCLK edge must be smaller than +/- 390 ns (FS/4) related to the datasheet entry. I think we can meet this condition. Is it ok, when BCLK and WCLK already running while codec initialization? In our case the 8 MHz signal (BCLK source) is running before codec is initialized. The WCLK signal (8 kHz) is running after initialization. We have noticed that approx. 380 ms of data is available via DOUT after start and then only 0 is sent. How can this behavior be explained? Normally everything should start again when the condition < FS/4 is faulty. We have set bit D1 and bit D0 in the register 34 (Page 0). If we set only bit D1 then data will be sent. However, data are not plausible. When we not use the re-sync functionality everything works fine, and data transmitted as expected.

Is it important to follow the correct order when writing the registers, (e.g.ADC power up – Reg 81) after Page 1 entries have been written (see data sheet)?


Best regards,


  • Hi Steffen,

    There shouldn't be any problems in initialization regardless of whether BCLK and FSYNC are running. Can you share your clock configuration for review? You typically shouldn't need to use the resynchronization feature unless you have excessive clock drift or other errors in the clock generation.

    Generally yes it is recommended to finish the ADC and PGA configurations prior to powering up to avoid any unwanted noise on the output from configuration.