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CDCE913: Start up problem

Guru 20550 points

Replies: 10

Views: 379

Part Number: CDCE913

Hi,

My customer says that the CDCE913 has start up problem before.

(Because I had not supported them at the time, I do not know the problem directly.)

The symptom is unstable oscillation.

Occurrence condition of the symptom are that

1. What SSC is on.

2. What to take over a few hundred ms until input clock supplied(they use FPGA to supply) after power supplied.

Does TI recognize the problem?

If yes, has this problem been already improved?

Best Regards,

Kuramochi

  • Which one is earlier?
    Input clock or power supply for CDCE913

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Shawn Han:

    Han-san,

    Thank you for your reply.
    Power supply is earlier.

    Best Regards,
    Kuramochi
  • In reply to Kuramochi Tadahiko:

    When reference is get ready, PLL would enter locking mode, locking is not locked, so output should be not stable.
    After PLL locked, output becomes stable.

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Shawn Han:

    Han-san,

    Thank you for your reply.

    What is relationship during your explanation and the problem my customer is saying?

    Best regards,
    Kuramochi
  • In reply to Kuramochi Tadahiko:

    Hi Kuramochi,
    I answered a reason for unstable output.
    Looks I didn't understand your customer's problem. Could you clarify the problems in your 1st post?

    "The symptom is unstable oscillation.
    Occurrence condition of the symptom are that
    1. What (When ?) SSC is on.
    2. What ( ?) to take over a few hundred ms until input clock supplied(they use FPGA to supply) after power supplied."

    Is that meaning when SSC is OFF, the unstable oscillation (output) would not happen?

    Regards,
    Shawn

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Shawn Han:

    Shawn-san,

    >Is that meaning when SSC is OFF, the unstable oscillation (output) would not happen?

    Yes, your understanding is correct.

    Best Regards,
    Kuramochi
  • In reply to Kuramochi Tadahiko:

    SSC is intentional phase modulation when it is enabled, so the output clock phase will appear unstable (like jitter) but the average frequency over time will be correct as it is configured. Did they use ClockPro to generate the configuration settings? How are they observing the "unstable behavior" (test equipment & setup)?

    The SCC modulation is dependent on the VCO frequency. See the attached SSC frequency modulation calculator workseet.
    e2e.ti.com/.../4137.CDCE9xx_5F00_SSC_5F00_Fmod_5F00_Calculator.xls

    Alan
  • In reply to Alan O:

    Alan-san,

    Thank you for your reply.
    I'll check it.

    Best Regards,
    Kuramochi
  • In reply to Alan O:

    Alan-san,

    Thank you for your help.
    I'll check them.

    Best Regards,
    Kuramochi
  • In reply to Kuramochi Tadahiko:

    Kuramochi-san,

    OK, we will await your response.

    Regards,
    Dean

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