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LMK05028: Input-to-output phase offset

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Replies: 15

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Part Number: LMK05028

Hello,

I have a question about LMK05028.

[Q]

What is the Min / MAX value of the input-to-output phase offset of the LMK05028?
I want to know the output phase difference between devices caused by Input-to-output phase offset.

Best Regards,

Kaede Kudo

  • In reply to Timothy T:

    Hello Timothy-san,

    Thank you for your comment.

    I understood what you are saying.

    However, what I am concerned about at this time is that the phase difference between the input and output is not deterministic.

    I corrected the points pointed out by you and observed the input and output waveforms again with an oscilloscope.

    /cfs-file/__key/communityserver-discussions-components-files/48/2262.190729_5F00_test_5F00_e2e.txt

    However, the phase of the output fluctuates relative to the phase of the input.
    - Yellow input
    - Blue OUT4_P
    - Pink OUT3_P

    Click here to play this video

    I was expecting that the input-to-output phase offset  was always deterministic by using it in ZDM, is my recognition wrong?

    Or is there something strange about the setting?

    Thank you for your confirmation.

    Best Regards,

    Kaede Kudo

  • In reply to Timothy T:

    Hello Kudo-san,

    I've confirmed your file.  I was able to measure deterministic phase between input and output.  This measurement was made from IN0_P to OUT4_P.

    • With your config, only OUT4_P will have deterministic phase because it is the only output with sync enabled (by CH45_SYNCEN = 1).
    • Note that OUT4 is also driven by DPLL1.  I noticed that DPLL2 is configured 10 Hz loop bandwidth and Wireless/BTS which has higher TDC rates and can take a longer time to for LOPF to go low because of the settings and the ratio of loop bandwidth to TDC rate.
    • I also confirmed that by entering a value into the Tph-offset (ns) it will produce a offset in the phase from input to output.

    I recommend the following updates:

    • Since you are using a simple 166.67 MHz input to 166.67 MHz output.  You only need a single DPLL to run.  So derive all outputs from DPLL1.
    • If you want all outputs to have aligned phase to input, we must enable SYNCEN on all outputs on the Advanced --> Outputs page.
    • Attached is a file with these updates.  190722_test_e2e_2, updated for PLL1 only with all SYNC on.tcs

    If you are having difficulty repeating the measurement for deterministic input to output phase, read the status bits and please confirm...

    • The reference is validated, REF0VALSTAT = 1 or REF1VALSTAT = 1.
    • The loss of frequency and phase lock bits are low.  DPLL?_LOFL = 0 and DPLL?_LOPL = 0
    • Depending on initial state, after programming (Ctrl + L), you may try doing a soft-reset chip by clicking the button in the top toolbar.

    73,
    Timothy

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect​​​​
    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Timothy T:

    Hello Timothy-san,

    Thank you for your cooperation!

    I tried your settings.
    However, the input to output phase offsets are not yet deterministic.
    The following contents were confirmed and executed, but it was useless.

    • The reference is validated, REF0VALSTAT = 1 or REF1VALSTAT = 1.
      ⇒I use input0. REF0VALSTAT=1
    • The loss of frequency and phase lock bits are low.  DPLL?_LOFL = 0 and DPLL?_LOPL = 0
      ⇒DPLL1_LOFL=0, DPLL1_LOPL=0
    • Depending on initial state, after programming (Ctrl + L), you may try doing a soft-reset chip by clicking the button in the top toolbar.
      ⇒I did, but the output phase difference is not deterministic and is fluctuating.

    I'm sorry, but please keep in touch a little more.

    * Can you tell us about the environment you evaluated?
    Ex) What is the reference input using?

    I will try to be as similar as possible to your evaluation environment and see if we can get similar results.

    Best Regards,
    Kaede Kudo

  • In reply to KAEDE KUDO:

    Hello Kudo-san,

    Here is an example plot from my setup.  I repeated this measurement 5 times, they all looked the same.

    CH1 (yellow) = IN0_P signal from Signal Generator.  I think it was a Rohde & Schwarz SMB100A.
    CH2 (green) = OUT1_P
    CH4 (pink) = OUT4_P

    * If you look at two outputs, as I did above.. can you confirm they have the same/deterministic phase to one another?

    * Please confirm that all the wave forms display properly, it is just from one lock, to the next lock that they change.
       - Can you share a plot of your signals as above?  And also a second illustrating how they shift?

    73,
    Timothy

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect​​​​
    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Timothy T:

    Hello Timothy-san,

    thank you for contacting.

    I was able to solve the problem and I was able to see deterministic delays in input and output.

    The reason was that the Reference I used had a wander.
    I was able to solve the problem by taking one of the following two measures.
    *Change Reference to Signal Generator output.
    *Expand LBW of DPLL1.

    Thank you for your cooperation!

    Best Regards,

    Kaede Kudo

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