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LMK05028: Input-to-output phase offset

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Replies: 15

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Part Number: LMK05028

Hello,

I have a question about LMK05028.

[Q]

What is the Min / MAX value of the input-to-output phase offset of the LMK05028?
I want to know the output phase difference between devices caused by Input-to-output phase offset.

Best Regards,

Kaede Kudo

  • Hello Kudo-san,

    I will get you a response tomorrow morning, sorry for the delay.

    Regards,

    Derek Payne

    Texas Instruments

  • Hello Kudo-san,

    The variation is approximately +/- 0.2 ns on a device.  Across process it would be a bit higher.

    73,
    Timothy

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect​​​​
    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Timothy T:

    Hello Timothy-san,

    Thank you for your cooperation!

    It was understood that the variation of the input-to-output phase offset can be seen as the phase difference of the output between multiple devices.

    Best Regards,

    Kaede Kudo

  • In reply to KAEDE KUDO:

    Hello Timothy-san,

    Let me ask you more questions.
    ・ Is Phase offset adjustable with DPLL1_REF_SYNC_PH_OFFSET?
    ・ Is the Phase Offset set by the above Register maintained even after the power is turned on again?
    ・ What is the resolution of the above Register settings?

    Best Regards,
    Kaede Kudo
  • In reply to KAEDE KUDO:

    Hello

    I have some more questions.
    Excuse me, could you help me with my question?

    I am now using LMK05028 EVM to check that the input to output offset is deterministic.
    However, I have not confirmed.
    Attach my status and configuration file below.
    How can I solve this problem?

    [problem]
    • The phase relationship between the output and the input is not a deereministic delay.
    • I observed the waveform of the output signal and the input signal with an oscilloscope.
    • I triggered the input signal.
    • At that time, the phase of the output signal was always fluctuating.

    [Expected behavior]
    • The phase relationship between input and output should be deterministic delay.

    [setting file]

    [Setting contents]
    • Input = 166.67 MHz
    • Output = 166.67 MHz
    •  2 Loop, REF, APLL
    •  ZDM = Enable
    •  LMK05028 EVM RevA1

    [Question]
    ・ Is there anything wrong with my settings?
    ・ Is the setting method of Zero Delay mode wrong?
    ・ Are there settings for DPLL TDC?

    Best Regards,

    Kaede Kudo

  • In reply to KAEDE KUDO:

    I'm sorry
    I did not attach a configuration file, so I thought that I would attach it here, but I can not insert TCS File.
    Please let me know if you know how to extract the configuration file.

    Best Regards,
    Kaede Kudo

  • In reply to KAEDE KUDO:

    Hello Kudo-san,

    If you rename the .tcs file to .txt, then you should be able to attach.

    My understanding is that E2E team was going to update to allow .tcs files to be attached, but appears to not been completed.

    73,
    Timothy

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect​​​​
    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Timothy T:

    Hello Timothy-san,

    Thank you for your comment.

    I got a text file.
    Thank you for your confirmation.

    190723_test_e2e.txt

    Best Regards,

    Kaede Kudo

  • In reply to KAEDE KUDO:

    Hello, 

    The previous was a Text File that exported Register data.
    I will send the File which changed .tcs to .txt again.

    190722_test_e2e_2.txt


    Thank you for your confirmation.

    Best Regards,

    Kaede Kudo

  • In reply to KAEDE KUDO:

    Hello Kudo-san,

    I presume you were making your measurement between the input and OUT4 or OUT5?

    I did not get to try your file in the lab at this time, I could do this next week if need be.  However I did observe that...

    1) Only channel 45 has SYNCEN = 1.  So the phase to other clocks outputs would not be deterministic.
    2) The 166.67 is coming from both DPLL1 and DPLL2.  I expect you would rather all the 166.67 MHz clocks come from a single DPLL so that you can then set for example PLL1_PRI_CH03_SYNC_BNK and PLL1_PRI_CH47_SYNC_BNK and have them all synchronized together.

    73,
    Timothy

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect​​​​
    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

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