Part Number: CDCE6214-Q1
Im use CDCE6214-Q1 recommended by you for jitter cleaner....
1: what is output jitter at 2MHz and 74.25MHz
2: In datasheet no details for un-used output pin because unused output create floating so, what we can do for this...
please check attached schematic in PDF and provide solution...
In reply to Hao Z:
please find attached layout image and check it, 74.25MHZ trace is too long it will create jitter and noise or not
i know 74.25MHz trace is long but no more option to route it...
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I see. I still recommend using ferrite bead to separate VDD pins, because VDD_REF can be very noisy (VDD for digital reference level), and VDD_VCO is very sensitive to noise. You don't want noise from reference and output to be coupled into VCO. Connecting VDDO_12 (VDD for output 1 and 2) and VDDO_34 can result in crosstalk between outputs if they have different frequencies, which is true in your case.
did you find a solution for this problem
2: In datasheet no details for un-used output pin because unused output create floating so, what we can do for this... !!
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In reply to snow jhon:
I use ferrite bead to separate VDD pins. see attached pdf...
my question is im use out0 bypass output 74.25MHz frequency, is trace very large in layout so it create noise (or jitter) in output or not ...
solution provided by you ( Unused outputs should be disabled in the software and left floating.)..
In reply to phew:
Y0 and Y1 are on the opposite sides so the crosstalk between the two will be minimal. However, you can always reduce the thickness of first layer in order to reduce the width of 74.25MHz trace, if that's what you mean by trace being very large.
For unused outputs, disable them in software and leave them open in schematic.
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