CDCLVD2102: Static input

Prodigy 120 points

Replies: 4

Views: 97

Part Number: CDCLVD2102

Is there any input condition that would cause the LVDS output to rail to 2.5Volts? (i.e. single static input)

4 Replies

  • Hello Jeffrey,

    Offhand, I'm not aware of any such condition... but let me make sure I understand what you're seeing:

    Do I understand that all outputs are 2.5 V?  That is all eight output pins from both inputs?
    Do I understand this is something you are seeing on a PCB you've designed?  Would you be able to share the schematic?

    Or perhaps you are seeing the high output pin as 2.5 V, while you would expect to see a maximum of max(Voc(ss)) + max(Vod/2) = 1.375 + 0.45/2 = 1.6 V.
      * What do you see on the other pin?  Lowest you'd expect to see is 1.1 V - 0.45 / 2 = 0.875 V.


    73,
    Timothy

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  • In reply to Timothy T:

    Hello Timothy,

    Tomorrow with a colleague, I am going to use an oscilloscope sending repeated data requests to see what the input/outputs of the CDCLVD2102 are doing in the system.  Our application uses this device to test ASICs.  The single ended inputs are converted to LVDS, then driven across a tester PCB through an FMC connector to a Xilinx based development board.  Our ASIC tests are the first for new devices...i.e. we are undergoing ASIC process and test development, thus, may experience erroneous inputs to the CDCLVD2102.  I  thought I would submit the question to your support site to see if in your and/or customers  have any experiences with the CDCLVD2102 where there was some input condition that may cause the output to drive to the supply rail.  Unfortunately, I can not share schematics, though the connections are straight forward:  single ended signals go into the INP0 and INP1 inputs.  The INN0 and INN1 inputs have independent voltage dividers providing 1.25V input.   GND and EP are connected to Ground.  The EN pin, OUTP1/OUTN1 and OUTP3/OUTN3 pins are not connected.  The power pin VCC is supplied with filtered +2.5V.  

  • In reply to Timothy T:

    Timothy,

    A folllow-up to your response to my question:  I noticed in the CDCLVD2102 that the absolute maximum Vout = –0.2 to (VCC + 0.2) V...i.e. 2.5+0.2 = 2.7.  On my tester, the CDCLVD2102 output is connected to Xilinx Virtex-7 1.8V LVDS inputs whose aboslute maximum voltage is 2.35V.  Thus, I was wondering if there was any condition (power-up, etc) that would cause the CDCLVD2102's outputs to go to 2.5-2.7V.  I did discover a condition in my test setup that would have caused the CDCLVD2102's single ended input to be tristate.  What would the output do in this condition?

  • In reply to Jeffrey McCasland:

    Thanks for the input.  I expect the condition you mention is EN = 0, which disables the outputs that causes the high impedance? --> Sorry you mentioned that EN is floating and input is tri-state.

    The datasheet mentions if one output is not used, to set EN=1, then ground the unused input with 1 kohm resistors.

    If the input is floating, I expect a risk of oscillation on the output.

    73,
    Timothy

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect​​​​
    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html