Hi,
IBIS Model for CDCLVD1212 seems to have some issue. We are connecting CDCM6208 output to this Clock Buffer @ 200MHz (LVDS). However the clock signal gets completely distorted. However if we replace IBIS model of CDCLVD1212 by CDCLVP1212, the signal is clean during SI analysis. Both these buffers must have identical input block. Hence we suspect that IBIS model for CDCLVD1212 is not correct.
Also in the model, pin 9 is shown as Negative input and pin 8 is shown as positive input which is not correct. Please change them as well
