Hi
I'm using a MSP430FG4617 with a Mclk and SMCLK Clock of 8 MHz (using DCO).
When only Initializeing the clock the output of the MCLK on P1 verifyes that the clock has 8 MHz.
The Problem:
when using the Timer B the clock collapses to approx. 6 MHz.
When also using ADC12 the clock slows down to only ~4 MHz
A coworker sugested to change the FN_x in SCFI0 - that didn't help.
Any Ideas?
My Code __________________________________________
/*
This code uses TimerB, ADC12, MPY and DAC.
// Inputs __________________________________________
P6.0 ADC12 - Left Channel
P6.1 ADC12 - Right Channel
// Outputs _________________________________________
P2.1 PWM Periode
P2.2 PWM Left
P2.3 PWM Right
P6.6 DAC output - Left Channel
P6.7 DAC output - Right Channel
// Registers _________________________________________
R10 used for Left Channel
R11 used for Right Channel
*/
#include <msp430fg4617.h>
#define STATUS R5
#define INT_ADC BIT1
#define INT_TB BIT2
;-------------------------------------------------------------------------------
RSEG CSTACK ; Define stack segment
;-------------------------------------------------------------------------------
RSEG CODE ; Assemble to Flash memory
;-------------------------------------------------------------------------------
main
RESET mov.w #SFE(CSTACK),SP ; Initialize stackpointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
call #INIT_MCLK_8MHz
call #INIT_ADC
call #INIT_PWM
call #INIT_DAC
call #Setup_MPY_Scaleing
EINT
bis.w #ENC+ADC12SC,&ADC12CTL0 ; Start sampling/conversion
xor.w STATUS, STATUS
LOOP nop
//bis.w #LPM1 + GIE, SR ; Not used for Testing
nop
xLOOP nop
AND.W #0x01E, STATUS
ADD.W STATUS, PC ; Bit 0 not used
JMP LOOP ; wenn nichts anliegt
JMP F_X00 ; 2
JMP F_X01 ; 4
JMP F_X00 ; 6
JMP LOOP
JMP LOOP
F_X00 CALL #ADC12_Work
BIC.W #INT_ADC,STATUS
JMP xLOOP
F_X01 NOP ; Not used
BIC.W #INT_TB, STATUS
JMP xLOOP
ADC12_Work
bis.b #BIT0,&P1OUT ; Toggle P1.0 ;debug
mov.w ADC12MEM0,&DAC12_0DAT
mov.w ADC12MEM1,&DAC12_1DAT
mov ADC12MEM0,R10
mov ADC12MEM1,R11
add ADC12MEM2,R10
add ADC12MEM3,R11
DINT
mov R10,&OP2 ; 1Q15 Fixpoint
NOP
EINT
mov.w RESHI, &TBCCR1
DINT
mov R11,&OP2 ; 1Q15 Fixpoint
NOP
EINT
mov.w RESHI,&TBCCR2
// bis.w #ENC+ADC12SC,&ADC12CTL0 ; Start next sampling/conversion
bic.b #BIT0,&P1OUT ; Toggle P1.0 ;debug
ret
//----------------------------------------------------------------------------
// --- INIT ------------------------------------------------------------------
//----------------------------------------------------------------------------
INIT_MCLK_8MHz
bis.b #FN_4,&SCFI0 ; x2 DCO, 8MHz nominal DCO
bis.b #DCOPLUS+XCAP14PF,&FLL_CTL0 ; DCO+, configure load caps
mov.b #121,&SCFQCTL ; (121+1) x 2 x 32768 = 7.999 Mhz
;; Output Clock
bis.b #0x32,&P1DIR ; P1.1, P1.4 & P1.5 to output direction
bis.b #0x32,&P1SEL ; P1.1 & P1.5 to output MCLK, SMCLK & ACLK
ret
INIT_ADC ;___________________________________________________________
bis.b #BIT0+BIT1,&P6SEL ; P6.0 and P6.1 ADC option select - debugging
mov.w #SHT0_0 + SHT1_0 + ADC12ON + REFON + REF2_5V + MSC,&ADC12CTL0
mov.w #SHP + ADC12SSEL_3 + CONSEQ_1,&ADC12CTL1
mov.w #08h,&ADC12IE ; Enable interrupt for MEM3
bis.b #INCH_0 + SREF_1 ,&ADC12MCTL0
bis.b #INCH_1 + SREF_1 ,&ADC12MCTL1
bis.b #INCH_0 + SREF_1 ,&ADC12MCTL2
bis.b #INCH_1 + SREF_1 + EOS ,&ADC12MCTL3 // Interrupt
bis.b #BIT6+BIT0,&P1DIR ; P1.0 and P1.6 to output direction - for debugging
bis.w #ENC,&ADC12CTL0
nop
ret
INIT_PWM ;___________________________________________________________
;Configure Outputs
bis.b #BIT1+BIT2+BIT3, P2DIR
bis.b #BIT1+BIT2+BIT3, P2SEL
; Setup Timer B
mov.w #TBSSEL_2+ID_0+MC_1,&TBCTL ; Timer B mit SMCLK im UP Mode
bic.w #TBIFG,TBCTL ; Clear Interrupt Flag
mov.w #179,&TBCCR0 ; Set f_PWM ca. 44,8 kHz
mov.w #CCIE+OUTMOD_7,&TBCCTL0
; Configure Left Channel PWM
mov.w #OUTMOD_7,&TBCCTL1 ; CCR1 reset/set
mov.w #0x00,TBCCR1
; Configure Right Channel PWM
mov.w #OUTMOD_7,&TBCCTL2 ; CCR1 reset/set
mov.w #0x00,TBCCR2
bis.b #BIT7,&P1DIR
ret
Setup_MPY_Scaleing ;___________________________________________________________
; Setup MPY to convert ADC Values to PWM Output
mov.w #1445,&MPY ; MPY first operand - 15Q1 Fixpoint
; OP2 is set later ba DMA
ret
INIT_DAC ;______________________________________________________________________
bis.b #BIT6+BIT7,&P6DIR ; Set Pin 6 and 7 as output
bis.b #BIT6+BIT7,&P6SEL ; Select special Function on Pin 6 and 7
bis.w #DAC12IR + DAC12AMP_5 + DAC12ENC, &DAC12_0CTL ; Int ref gain 1
bis.w #0x0000,DAC12_0DAT
bis.w #DAC12IR + DAC12AMP_5 + DAC12ENC, &DAC12_1CTL ; Int ref gain 1
bis.w #0x0000,&DAC12_1DAT
ret
//----------------------------------------------------------------------------
// --- INTERRUPT -------------------------------------------------------------
//----------------------------------------------------------------------------
;-------------------------------------------------------------------------------
ADC12_ISR;
;-------------------------------------------------------------------------------
bis.b #BIT6,&P1OUT ; Toggle P1.6 ; debug
bis.w #INT_ADC,STATUS
bic.w #LPM1,0(SP)
xor &ADC12IFG,&ADC12IFG ; Interrupt Flag cleared
bic.b #BIT6,&P1OUT ; Toggle P1.6 ; debug
reti
;------------------------------------------------------------------------------
TB_ISR ; ISR for TimerB
;------------------------------------------------------------------------------
bis.b #BIT7,&P1OUT ; debug
//bis.w #INT_TB,STATUS ; not needed - noting to do
//bic.w #LPM1,0(SP) ; not needed
bic.w #TBIFG,&TBCTL ; Clear TB interrupt flag
bis.w #ADC12SC,&ADC12CTL0 ; Start next sampling
bic.b #BIT7,&P1OUT ;debug
reti
;-------------------------------------------------------------------------------
COMMON INTVEC ; Interrupt Vectors
;-------------------------------------------------------------------------------
ORG ADC12_VECTOR ; ADC12 Vector
DW ADC12_ISR
ORG TIMERB0_VECTOR ; TimerB Vector
DW TB_ISR
ORG RESET_VECTOR ; POR, ext. Reset
DW RESET
END