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Hello. We are looking for a 10 MHz receiver with minimum jitter to synchronize/lock all a transceiver system. There are two inputs to select from, one is a 50 ohm SW input with levels above 0 dBm, the other being a LVCMOS-3.3V internal oscillator. Two outputs are needed (LVPECL 3.3V) and one of them will drive a TI/National clock synthesizer LMK04805 that will make 2 frequency conversions to generate a final clock in teh range of 2GHz.
We have preselected as first option LMK00304 and as second CDCLVP1204, but some questions arise when we compose the puzzle.
a) The LMK00304 specifies jitter for 3V/ns input slew rate (the output jitter is worst in the curves when the SR is smaller). The sinusoidal input SR is much smaller (not greater than 0.4V/ns with the help of transformers, etc.). The LVCMOS oscillator SR is specified 4ns, so obviously it's also not so good as the LMK00304 asks for. This has created us the need of inserting a clock buffer at each input to increase the SR of the LMK00304 input signals and be sure LMK00304 will perform at its best output jitter. (rise/fall a few hundred ps in PECL). But we need this waay 3 chips.
b) We decided in favour on LMK00304 instead CDCLVP1204 for several reasons, one of them is that the former seems to be newer, other that the latter data sheet lacks many details that the LMK00304 does include, as PSRR, input isolation, and even the output jitter is defined only for certain frequencies and voltages, without specifying any SR. There are no curves of jitter or noise floor vs. input slew rate for the 1204 as in the 00304 data sheet. But the LMK00304 is a larger chip and as drawback also it asks for 3V/ns, which creates the doubt if at this low frequency the 1204 can serve better.. And at the end, the jitter figures of 1204 for the same frequencies, with small input amplitudes, are not worst than the LMK00304 ones...
To complicate more any comparison (and decide if this scheme is even absurd at some respect) we are not happy because the LMK04805 asks only for 0.15V/ns, so it has not a lot of sense to interpose between the oinput and the final clock a reference distributor with comparable jitter but much more requiring in input SR... in fact the LMK04805 has 2selectable clock inputs, which could be used to avoid any previous multiplexing, but unfortunately, our design is a particular one and the 2nd clock input is devoted to work as "Fin" because we need to receive as PLL2 reference an external signal different than the oscillator locked by PLL1.
I consider a) using LMK00304 with the 2 input buffers (this is what we have now, but it has large power consumption and the relatively absurd SR/jitter budget commented), b) using CDCLVP1204 with the 2 input buffers (it could reduce the HW size) and even better 3) using CDCLVP1204 without the input buffers, if it is possible to get good output jitter from it when the active input is the 10 MHz 0dBm 50 ohm and also when it is the LVCMOS 3.3 V internal XO (whcih maximum load is around 600 ohm). One of the 1204 or 00304 differential LVPECL outputs will be driven to the LMK04805.
But the TI web is a large forest an maybe I missed other better chances, can you propose something better? In particular I wonder if there is any other LMK distributor that asks only 0.15V/ns like 04805 for optimum output jitter.
Corrections on my assumptions, evaluation of the alternatives and new sugegstions would be highly appreciated.
Here is the data for different input slew rates of CDCLVP1204 at 100MHz. The inherent noise floor of CDCLVP1204 is around -160dBc/Hz. So you will be limited by it at 10MHz. This will put the total jitter around 1ps, rms in 10kHz-20MHz range. Would this work?
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