Greetings,
I have designed the LMX2492-Q1 into a synthesizer assembly and I am currently testing the assembled prototypes to wring out any problems before we go into production.
The LMX2492 is tuning a broad band VCO by way of an inverting gain active loop filter. The wide band nature of the VCO also brings along with it significant Kvco variation over the frequency band. So, I planned on using the LMX2492 Charge Pump Gain adjustment register to compensate the loop filter bandwidth for the variation in Kvco. This technique has functioned very well in the past using other PLL ICs.
Also, I am currently using the Codeloader 4 software and USB2ANY dongle to program the LMX2492 (which works very well).
I have encountered two problems in accomplishing this.
1) The first was that the datasheet showed the Charge Pump Polarity bit (CPPOL) as needing to be programmed to 0 for a negative slope VCO and 1 for a positive slope VCO. I found my LMX2492 needing to be programmed opposite to this instruction. While my VCO itself has a positive tuning slope, the inverting gain active loop filter presents a negative tuning slope to the LMX2492. Therefore, I tried programming CPPOL to 0 first (in accordance with the datasheet). The unit would not lock and after some debugging I tried programming CPPOL to 1 and it locked up just fine. This is not really a showstopper for me because I just assumed it was a typo in the datasheet (which is Revision A - June 2014). I just wanted to point it out and ask if it has been reported and if it is going to be corrected on the next datasheet revision?
2) The second problem is much more of a problem and is preventing me from moving forward towards production of the synthesizer.
Some background details first. Over the frequency range that I am tuning my VCO, the Kvco varies from a maximum of about 450 MHz/V to a minimum of about 200 MHz/V and I am targeting keeping the loop bandwidth at about 500 KHz (because the application needs fast switching speed). So, I designed and installed the loop filter components themselves using the loop filter topology shown below. Note also that I am using a low-noise FET input OpAmp to keep the leakage current out of the charge pump as low as possible. Also, I am using the LMX2492 in "integer" mode with phase detector frequency of 10 MHz. Also, the LMX2492 ICs are marked with lot code "44U AE21".
Now, the problem that I am experiencing is when I step through the sequential values of the Charge Pump Gain register (CPG). The LMX2492 datasheet quite clearly indicates that CPG of 1 programs the charge pump state to 0.1 mA, CPG of 2 programs the charge pump state to 0.2 mA, etc. up to CPG of 31 programs the charge pump state to 3.1 mA. From experience, I expect that changes to the charge pump current in a monotonic direction should change the loop bandwidth of the PLL in a monotonic direction. However, as I step the CPG register from 1 to 2 to 3 to 4 etc. I do not see the loop bandwidth moving in a monotonic direction. Note that I am judging the "loop bandwidth" from a plot of the locked synthesizer phase noise (on a very high quality phase noise measurement system). I also know that the reference phase noise and VCO phase noise are both well below the curve I am seeing on the final phase noise measurement. The only real contributors over the range of about 1 KHz to about 10 MHz offsets are the PLL chip phase noise and the active loop filter phase noise.
For example, I program the synthesizer to 6000 MHz (reference of 100 MHz , Fpfd of 10 MHz) and set CPG to 1 (which I assume equates to 0.1 mA) and my phase noise plot looks like a loop filter bandwidth of about 100 KHz. Then I step the CPG up to 2 and the phase noise plot looks like a loop filter bandwidth went up to about 500 KHz. Then I step up the CPG to 3 and the loop bandwidth moves down to about 300 KHz (which is opposite the expected direction). Then I step the CPG up to 4 and the loop bandwidth moves down to about 200 KHz (which is opposite the expected direction). Then I step the CPG up to 5 and the loop bandwidth moves up to about 400 KHz. Then I step up CPG to 6 and the loop bandwidth moves down to about 350 kHz (which is opposite the expected direction). Continuing on provides a similar pattern of increasing and decreasing of the loop bandwidth when the CPG is increased monotonically.
Moreover, the pattern of increasing and decreasing seems to change at different output frequencies. So, 6000 MHz had up, down, down, up, down response to CPG monotonic incrimintation from 1 to 6, but 5500 MHz might have a different pattern such as up, up, down, up, down when programmed over the same sequence of CPG.
As I stated before, my general experience is that the monotonically increasing charge pump current monotonically increases loop bandwidth, but the loop bandwidth appears to be hopping around as I monotonically increment the LMX2492 charge pump current.
Can you help me to understand this behavior because I cannot confidently move forward with production as it stands?
Is there a chance that the chips I have are bad? I am happy to provide additional details if necessary.
Thanks in advance for any assistance.
