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LMX2492 Passive and Active Filter on EVM

Jeffrey Roby
Prodigy 120 points
Other Parts Discussed in Thread: LMX2492, LM6211

Q1:

LMX2492  Data Sheet p28, the EVM is designed with PLL parameters (Kvco=200MHz/V, BW=380KHz, R=1, N=96, Kcp=??, Fin=100MHz, VccCP=5V) resulting in loop filter R's and C's listed in the table.

Entered the PLL parameters into Clock Design Tool I don't get the EVM Loop filter Cap and Resistors values listed. What is the reason?

Q2:

Also I would like to transition to an active filter(LM6211) to accommodate a wide band VCO with low Kvco=50MHz/V  and a wider tuning range 0 to 15 Volts. How is an Active filter design entered into Clock Design Tool? How will it cover the tuning range since VccCP=5Vmax? What Kvco value do I enter (50MHz/V or 3*50MHz/V) into the VCO section of the Design Tool?

Thanks.

  • 0
    TI__Mastermind 27581 points

    Jeffry,

    Q1:

    Kcp = 3.1 mA

    I entered the resistor cap values as stated and it came back with 377.5 kHz loop bandwidth, which is basically as claimed.

    But I think that you are going the other way of trying to enter the parameters and getting a loop filter.  Problem is that you don't have all the information to find a unique set of components.   The datasheet only gives the loop bandwidhth, which is one constraint.  The 3rd order loop filter has 5 components, and therefore needs 5 constraints, which are:   Loop Bandwidth, Phase Margin, Gamma, T3/T1 Ratio, and also to maximize C3.  Clock design tool "simplifies" things by hiding these parameters from you and this is probably the reason for the difference.  Our new clock architect on WebBench does expose tehse parameters in advanced mode.

    Q2:

    Clock design tool does not do active filters, but the clock architect on WebBench does.   So I would use this tool.  In general, the concept is to bias the charge pump at some nice voltage of about 2.5 V, but then the output of the op amp goes up to 15 V.   

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Prodigy 120 points
    Dean,
    Thanks for the reply, what are the EVM missing parameters (Phase Margin, Gamma, T3/T1 Ratio, and also to maximize C3)?
    My application is a sweep what is best for the loop filter.
    The Web bench Clock Architect page shows Active filter design as "Coming" and the Easy PLL doesn't support LMX2492.
    With Web Bench Clock I enter a 100MHz reference, 10GHz output , Enter Part Filter ?? and clock Generate button, "noSolution could be found"