Other Parts Discussed in Thread: AFE58JD18EVM, AFE5818EVM, CODELOADER
Hi,
I am setting up the LMK04826B on an AFE58JD18EVM board ( I know the "JD" is in a NDA category but the AFE5818EVM is setup the same, I think and this is about LMK ). I do not have the TSW1400 EVM or TSW14J56 EVM boards - the concept is to use the AFE EVM with a Xilinx FPGA. The board does not allow full SPI control from FMC so I have written code to control SPI from USB ( no problems here, I have validated this repeatedly and have 0 concerns about controlling this way).
My problem is setting up the LMK part. I have used the TI CodeLoader to generate register maps, I have used the HMC-DAQ setup script register maps ( in install directory ), and have setup registers repeatedly by hand.
* All registers readback properly ( using RESET pin on LMK )
* using board LEDs I can see that PLL1 locks, and PLL2 locks after VCO calibration
* If I don't calibrate VCO ( no PLL2 lock of course ) the output looks sane.
* If I calibrate VCO the output is not sane but after 10-15 minutes it outputs what you would expect (took awhile to accidentally notice this behavior)
After VCO calibration, I get output as shown below (multiple triggers so you can see that output pulse is not always the same):
This is two separate channels. After about 10-15 minutes:
I have experimented extensively with configuring the output channels but with the same results.
Some more info:
* 100 MHz VCXO
* using VCO1 @ 2500 MHz
* PLL2 feedback is using N2 Prescaler = 5, N2 divider = 5
Thanks - I'm mystified - the device shows lock the whole time (calibrated). This board did have an issue out of the box - the Crystek VCXO had a bad solder joint and needed to be reworked.