CDCE813-Q1: CDCE813 acknowledges only I2C read, not write.

Wolfgang Hennig

Part Number: CDCE813-Q1

I'm using the CDCE813-Q1 as a clock buffer/PLL and noticed 2 things

1) Contrary to the datasheet, it does not come up in the default "pass through" mode -- there is no clock out. (In is 25 MHz 1.8V CMOS)

2) Trying to program the IC via I2C to make it work, I notice the IC does not respond with a slave acknowledge after address + write, only after address + read.

Details on 2): My I2C bus master is an FPGA into which bits for SCL and SDA (and SDA tristate) are written by a processor executing a C program. Bits change on a ~100us time scale, with ~200 ns rise times. This works well on other I2C chips on the bus. What I'm sending is the sequence shown in Figure 9 of the datasheet:

Start

Addr+w = 11001010

clock for acknowledge, but no slave response

command code 1000 0000 for byte read from addr 0

clock for acknowledge, but no slave response

Start again

Addr+r = 11001011

clock for acknowledge, with slave response

clocks for slave read, returns 00000111

Stop

I'm fairly sure I have the correct slave address, since when I change it I get 11111111 in the last step. If I change the address in the command code, I still only get 00000111.

Any hints on what could be wrong would be appreciated.

over 6 years ago

0 Alan O over 6 years ago

TI__Mastermind 32575 points

Hello,
1) Can you check if toggling S0 (output enable) allows the clock to be enabled on Y1? Y2 and Y3 are disabled by default.
2) Can you screen captures from an o-scope / I2C analyzer of the SDA/SCL waveforms for write and read transactions along with the intended programming sequences to confirm what is happening? Have you confirmed the waveforms are compliant to the I2C specs in the datasheet?

Thanks,
Alan

0 Wolfgang Hennig over 6 years ago in reply to Alan O

Prodigy 60 points

Thank you for the quick answer.

My I2C routines did not have an explicit falling edge for SCL after the last data [or R/W] bit; instead SCL was driven low and SDA tristated at the same time for the acknowledge signal. So a subtle timing issue of the SCL falling edge -- apparently worked for the other ICs but not the CDCE813. With that fixed, I could see a proper acknowledge from the CDCE813 and can now read/write the registers.

There were 3 discrepancies to the default register values from the datasheet:
- reg 0x01: bits for A1,A0 are 01, not 00 as per table 11, but that is just a typo in table 11 (it's correct as 01 in table 7)
- reg 0x02: I read 0x94, table 11 says 0x9C. That means both Y1 states Y1_ST0 and Y1_ST1 are defined as "01 – Y1 disabled to Hi-Z state"
- reg 0x15: I read 0x00, table 12 says 0x02. Only affects Y2/3 .

S0 is tied to 1.8V with a 1.5K resistor, I can not toggle it. But correcting reg 0x02 to 0x9C enabled the output. The device is now working correctly. Not sure how it came up in the disabled state as the default; I tried on several boards and they all behaved the same.

Thanks again

Wolfgang

BTW, another datasheet typo is in section 9.3.4; the link to table 7 should be to table 8.

0 Alan O over 6 years ago in reply to Wolfgang Hennig

TI__Mastermind 32575 points

Thanks for your feedback and confirming things are working now.
Regards,
Alan

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CDCE813-Q1: CDCE813 acknowledges only I2C read, not write.