CDCE913: clocking for sigma delta adc

jack daniels

Part Number: CDCE913
Other Parts Discussed in Thread: CDCLVC1103

Hi,

I have an application where I need to drive 3 20 bit sigma delta ADC's with a clock. I was originally using a CMOS oscillator with a 45% - 55% duty cycle specification thru a CDCLVC1103 buffer. The concern was that running through the buffer would further degrade the duty cycle specification. I was then looking at the CDCE913 as an option as per the datasheet it does not seem to have duty cycle degradation. The desire was to run it in PLL bypass mode, but there does not seem to be any information on if running in bypass mode has any effect on the specifications. Can you advise if the CDCE913 is a better way to go, or is there another product that would work better?

over 6 years ago

0 Lane Boyd over 6 years ago

TI__Genius 16845 points

Hi Jack,

CDCLVC1103 datasheet Table 6.6 indicates that maximum pulse skew is 180ps @ VDD = 3.3V, or 220ps @ VDD = 2.5V for a 50% input duty cycle clock.

Table Note 1 beneath Table 6.6 gives the equation for estimating output duty cycle (odc). Simply use this equation to determine duty cycle of the buffer output clocks.

For example, if you have a 100MHz CMOS oscillator clock input with 45% percent duty cycle, and VDD = 3.3V:

t_w(out) = 0.45 / 100MHz = 4.5 ns
t_sk(p) = 180ps
odc = [ 4.5ns +/- 180 ps ] * 100MHz
odc = { 46.8% , 43.2% }
duty cycle degradation = 46.8% - 45% =
duty cycle degradation = 1.8%

Please calculate the duty cycle at your operating points and see if this meets your requirements.

Kind regards,
Lane Boyd

Clock & timing

Clock & timing forum

CDCE913: clocking for sigma delta adc